Lines Matching +full:0 +full:x01c40000
28 #define MDSTAT_STATE 0x3f
37 mov r1, $0
57 orr r7, r7, $0x02
64 ands r7, r7, $0x02
71 ands r7, r7, $0x100
77 mov r10, $0
84 mov r10, $0x01
92 mov r10, $0
100 mov r10, $0
120 mov r10, $0x20
142 mov r2, $0x17 /* 162 MHz */
147 mov r3, $0x01
152 mov r4, $0x0b /* 54 MHz */
160 mov r9, $0x01
168 orr r7, r7, $0x01
175 ands r7, r7, $0x01
183 mov r9, $0x01
191 orr r7, r7, $0x01
198 ands r7, r7, $0x01
202 mov r10, $0x218
210 orr r8, r8, $0x08
222 orr r8, r8, $0x01
234 orr r7, r7, $0x03
240 orr r7, r7, $0x01
247 ands r7, r7, $0x01
255 cmp r7, $0x03
272 /* Program SDRAM TIM-0 Config Register */
309 orr r7, r7, $0x01
315 orr r7, r7, $0x01
322 ands r7, r7, $0x01
330 cmp r7, $0x01
340 orr r7, r7, $0x03
346 orr r7, r7, $0x01
353 ands r7, r7, $0x01
361 cmp r7, $0x03
366 mov r3, $0x01
374 mov r2, $0
394 mov r10, $0x20
406 orr r8, r8, $0x10
421 mov r3, $0x15 /* For 594MHz */
425 mov r10, $0xff
433 orr r8, r8, $0x08
444 orr r8, r8, $0x01
501 mov r10, $0x01
527 mov r10, $0
540 .word 0x01c40000 /* Device Configuration Registers */
542 .word 0x01c40004 /* Device Configuration Registers */
545 .word 0x00000c1f
548 .word 0x01e00004
550 .word 0
552 .word 0x01e00014
554 .word 0x3ffffffd
556 .word 0x01e00018
558 .word 0x3ffffffd
560 .word 0x01e0001c
562 .word 0x3ffffffd
565 .word 0x01c41a34
567 .word 0x01c41834
570 .word 0x01c41120
572 .word 0x01c41128
575 .word 0x01c48018
577 .word 0x01c4801c
580 .word 0xffffffe0
582 .word 0xfffffeff
586 .word 0x200000e4
588 .word 0x50006405
590 .word 0x2000000c
592 .word 0x000005c3
594 .word 0x20000008
597 .word 0x00178622
599 .word 0x00178632
604 .word 0x20000010
606 .word 0x28923211
608 .word 0x20000014
610 .word 0x0016c722
612 .word 0x200000f0 /* VTP IO Control register */
614 .word 0x01c42030 /* DDR VPTR MMR */
616 .word 0x201f
618 .word 0xa01f
620 .word 0x01c4004c
622 .word 0x5b0
624 .word 0xffffdfff
626 .word 0x08000
628 .word 0x02000
630 .word 0x80010000
632 .word 0x00000fff
636 .word 0x01c41a9c
638 .word 0x01c4189c
642 .word 0x01c41a20
645 .word 0xfffffeff /* Mask the Clock Mode bit */
647 .word 0xffffffdf /* Select the PLLEN source */
649 .word 0xfffffffe /* Put the PLL in BYPASS */
651 .word 0xfffffff7 /* Put the PLL in Reset Mode */
653 .word 0xfffffffd /* PLL Power up Mask Bit */
655 .word 0xffffffef /* Enable the PLL from Disable */
657 .word 0x2000
661 .word 0x01c40900
663 .word 0x01c40910
667 .word 0x01c40d00
669 .word 0x01c40d10
671 .word 0x01c40d18
673 .word 0x01c40d1c
675 .word 0x01c40d38
677 .word 0x01c40d3c
679 .word 0xffff7fff
682 .word 0x01c42010 /* BRF margin mode 0 (R/W)*/
684 .word 0x00444400
687 .word 0x80000000
689 .word 0xa55aa55a