Lines Matching +full:0 +full:x01c70000
35 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)
36 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
37 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
38 #define DAVINCI_UART0_BASE (0x01c20000)
39 #define DAVINCI_UART1_BASE (0x01c20400)
40 #define DAVINCI_TIMER3_BASE (0x01c20800)
41 #define DAVINCI_I2C_BASE (0x01c21000)
42 #define DAVINCI_TIMER0_BASE (0x01c21400)
43 #define DAVINCI_TIMER1_BASE (0x01c21800)
44 #define DAVINCI_WDOG_BASE (0x01c21c00)
45 #define DAVINCI_PWM0_BASE (0x01c22000)
46 #define DAVINCI_PWM1_BASE (0x01c22400)
47 #define DAVINCI_PWM2_BASE (0x01c22800)
48 #define DAVINCI_TIMER4_BASE (0x01c23800)
49 #define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
50 #define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
51 #define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
52 #define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
53 #define DAVINCI_ARM_INTC_BASE (0x01c48000)
54 #define DAVINCI_USB_OTG_BASE (0x01c64000)
55 #define DAVINCI_CFC_ATA_BASE (0x01c66000)
56 #define DAVINCI_SPI_BASE (0x01c66800)
57 #define DAVINCI_GPIO_BASE (0x01c67000)
58 #define DAVINCI_VPSS_REGS_BASE (0x01c70000)
60 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
61 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
62 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
63 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
65 #define DAVINCI_DDR_BASE (0x80000000)
68 #define DAVINCI_UART2_BASE 0x01c20800
69 #define DAVINCI_UHPI_BASE 0x01c67800
70 #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
71 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
72 #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
73 #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
74 #define DAVINCI_IMCOP_BASE 0x01cc0000
75 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
76 #define DAVINCI_VLYNQ_BASE 0x01e01000
77 #define DAVINCI_ASP_BASE 0x01e02000
78 #define DAVINCI_MMC_SD_BASE 0x01e10000
79 #define DAVINCI_MS_BASE 0x01e20000
80 #define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
83 #define DAVINCI_MMC_SD1_BASE 0x01e00000
84 #define DAVINCI_ASP0_BASE 0x01e02000
85 #define DAVINCI_ASP1_BASE 0x01e04000
86 #define DAVINCI_UART2_BASE 0x01e06000
87 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
88 #define DAVINCI_MMC_SD0_BASE 0x01e11000
91 #define DAVINCI_MMC_SD1_BASE 0x01d00000
92 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
93 #define DAVINCI_MMC_SD0_BASE 0x01d11000
94 #define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000
95 #define DAVINCI_SPI0_BASE 0x01c66000
96 #define DAVINCI_SPI1_BASE 0x01c66800
99 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
100 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
101 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
102 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
103 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
109 #define DAVINCI_UART0_BASE 0x01c42000
110 #define DAVINCI_UART1_BASE 0x01d0c000
111 #define DAVINCI_UART2_BASE 0x01d0d000
112 #define DAVINCI_I2C0_BASE 0x01c22000
113 #define DAVINCI_I2C1_BASE 0x01e28000
114 #define DAVINCI_TIMER0_BASE 0x01c20000
115 #define DAVINCI_TIMER1_BASE 0x01c21000
116 #define DAVINCI_WDOG_BASE 0x01c21000
117 #define DAVINCI_RTC_BASE 0x01c23000
118 #define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
119 #define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
120 #define DAVINCI_PSC0_BASE 0x01c10000
121 #define DAVINCI_PSC1_BASE 0x01e27000
122 #define DAVINCI_SPI0_BASE 0x01c41000
123 #define DAVINCI_USB_OTG_BASE 0x01e00000
125 0x01e12000 : 0x01f0e000)
126 #define DAVINCI_GPIO_BASE 0x01e26000
127 #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
128 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
129 #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
130 #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
131 #define DAVINCI_SYSCFG1_BASE 0x01e2c000
132 #define DAVINCI_MMC_SD0_BASE 0x01c40000
133 #define DAVINCI_MMC_SD1_BASE 0x01e1b000
134 #define DAVINCI_TIMER2_BASE 0x01f0c000
135 #define DAVINCI_TIMER3_BASE 0x01f0d000
136 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
137 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
138 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
139 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
140 #define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
141 #define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
142 #define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
143 #define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
144 #define DAVINCI_INTC_BASE 0xfffee000
145 #define DAVINCI_BOOTCFG_BASE 0x01c14000
146 #define DAVINCI_LCD_CNTL_BASE 0x01e13000
147 #define DAVINCI_L3CBARAM_BASE 0x80000000
148 #define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
149 #define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24)
150 #define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44)
151 #define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00)
153 #define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10)
154 #define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14)
155 #define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18)
156 #define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c)
157 #define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
158 #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
159 #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
160 #define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
161 #define GPIO_BANK6_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x88)
162 #define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c)
163 #define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90)
164 #define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94)
168 #define DAVINCI_GPSC_ARMDOMAIN 0
173 #define DAVINCI_LPSC_VPSSMSTR 0
225 #define DAVINCI_LPSC_TPCC 0
270 #define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0)
302 #define PSC_CHP_SHRTSW (0x01c40038)
303 #define PSC_GBLCTL (0x01c41010)
304 #define PSC_EPCPR (0x01c41070)
305 #define PSC_EPCCR (0x01c41078)
306 #define PSC_PTCMD (0x01c41120)
307 #define PSC_PTSTAT (0x01c41128)
308 #define PSC_PDSTAT (0x01c41200)
309 #define PSC_PDSTAT1 (0x01c41204)
310 #define PSC_PDCTL (0x01c41300)
311 #define PSC_PDCTL1 (0x01c41304)
313 #define PSC_MDCTL_BASE (0x01c41a00)
314 #define PSC_MDSTAT_BASE (0x01c41800)
316 #define VDD3P3V_PWDN (0x01c40048)
317 #define UART0_PWREMU_MGMT (0x01c20030)
319 #define PSC_SILVER_BULLET (0x01c41a20)
323 #define PSC_ENABLE 0x3
324 #define PSC_DISABLE 0x2
325 #define PSC_SYNCRESET 0x1
326 #define PSC_SWRSTDISABLE 0x0
331 #define UART0_PWREMU_MGMT (0x01c42030)
359 #define PSC_MDSTAT_STATE 0x3f
360 #define PSC_MDCTL_NEXT 0x07
365 #define VBPR (0x20000020)
370 #define PINMUX0 0x01c40000
371 #define PINMUX1 0x01c40004
372 #define PINMUX2 0x01c40008
373 #define PINMUX3 0x01c4000c
374 #define PINMUX4 0x01c40010
383 #define DAVINCI_UART_CTRL_BASE 0x28
386 #define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
427 #define DAVINCI_PLLC_DIV_MASK 0x1f
436 #define DAVINCI_PLLC0_FLAG (0)
459 DAVINCI_PLLM_CLKID = 0x0FF,
462 DAVINCI_PLLC_CLKID = 0x100,
465 DAVINCI_AUXCLK_CLKID = 0x101,
503 DAVINCI_NAND8_BOOT = 0b001110,
504 DAVINCI_NAND16_BOOT = 0b010000,
505 DAVINCI_SD_OR_MMC_BOOT = 0b011100,
506 DAVINCI_MMC_ONLY_BOOT = 0b111100,
507 DAVINCI_SPI0_FLASH_BOOT = 0b001010,
508 DAVINCI_SPI1_FLASH_BOOT = 0b001100,
545 #define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13
546 #define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0
571 #define DAVINCI_UART_CTRL_BASE 0x28
584 #define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
591 unsigned short part_no = (jtag_id >> 12) & 0xffff; in cpu_is_da830()
593 return ((part_no == 0xb7df) ? 1 : 0); in cpu_is_da830()
598 unsigned short part_no = (jtag_id >> 12) & 0xffff; in cpu_is_da850()
600 return ((part_no == 0xb7d1) ? 1 : 0); in cpu_is_da850()
605 return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ? in get_async3_src()
620 #define TMPBUF 0x00017ff8
621 #define TMPSTATUS 0x00017ff0
622 #define DV_TMPBUF_VAL 0x591b3ed7
623 #define FLAG_PORRST 0x00000001
624 #define FLAG_WDTRST 0x00000002
625 #define FLAG_FLGON 0x00000004
626 #define FLAG_FLGOFF 0x00000010