Lines Matching +full:0 +full:xf001c000
15 #define ATMEL_ID_FIQ 0 /* FIQ Interrupt */
21 #define ATMEL_ID_USART0 6 /* USART 0 */
23 #define ATMEL_ID_DMA0 8 /* DMA Controller 0 */
40 #define ATMEL_ID_UART0 27 /* UART 0 */
45 #define ATMEL_ID_TWI0 32 /* Two-Wire Interface 0 */
48 #define ATMEL_ID_MCI0 35 /* High Speed Multimedia Card Interface 0 */
50 #define ATMEL_ID_SPI0 37 /* Serial Peripheral Interface 0 */
53 #define ATMEL_ID_TC0 40 /* Timer Counter 0 (ch. 0, 1, 2) */
61 #define ATMEL_ID_SSC0 48 /* Synchronous Serial Controller 0 */
67 #define ATMEL_ID_GMAC0 54 /* Ethernet MAC 0 */
83 #define ATMEL_BASE_LCDC 0xf0000000
84 #define ATMEL_BASE_DMAC1 0xf0004000
85 #define ATMEL_BASE_ISI 0xf0008000
86 #define ATMEL_BASE_PKCC 0xf000C000
87 #define ATMEL_BASE_MPDDRC 0xf0010000
88 #define ATMEL_BASE_DMAC0 0xf0014000
89 #define ATMEL_BASE_PMC 0xf0018000
90 #define ATMEL_BASE_MATRIX0 0xf001c000
91 #define ATMEL_BASE_AESB 0xf0020000
92 /* Reserved: 0xf0024000 - 0xf8000000 */
93 #define ATMEL_BASE_MCI0 0xf8000000
94 #define ATMEL_BASE_UART0 0xf8004000
95 #define ATMEL_BASE_SSC0 0xf8008000
96 #define ATMEL_BASE_PWMC 0xf800c000
97 #define ATMEL_BASE_SPI0 0xf8010000
98 #define ATMEL_BASE_TWI0 0xf8014000
99 #define ATMEL_BASE_TWI1 0xf8018000
100 #define ATMEL_BASE_TC0 0xf801c000
101 #define ATMEL_BASE_GMAC0 0xf8020000
102 #define ATMEL_BASE_TWI2 0xf8024000
103 #define ATMEL_BASE_SFR 0xf8028000
104 #define ATMEL_BASE_USART0 0xf802c000
105 #define ATMEL_BASE_USART1 0xf8030000
106 /* Reserved: 0xf8034000 - 0xfc000000 */
107 #define ATMEL_BASE_MCI1 0xfc000000
108 #define ATMEL_BASE_UART1 0xfc004000
109 #define ATMEL_BASE_USART2 0xfc008000
110 #define ATMEL_BASE_USART3 0xfc00c000
111 #define ATMEL_BASE_USART4 0xfc010000
112 #define ATMEL_BASE_SSC1 0xfc014000
113 #define ATMEL_BASE_SPI1 0xfc018000
114 #define ATMEL_BASE_SPI2 0xfc01c000
115 #define ATMEL_BASE_TC1 0xfc020000
116 #define ATMEL_BASE_TC2 0xfc024000
117 #define ATMEL_BASE_GMAC1 0xfc028000
118 #define ATMEL_BASE_UDPHS 0xfc02c000
119 #define ATMEL_BASE_TRNG 0xfc030000
120 #define ATMEL_BASE_ADC 0xfc034000
121 #define ATMEL_BASE_TWI3 0xfc038000
123 #define ATMEL_BASE_MATRIX1 0xfc054000
125 #define ATMEL_BASE_SMC 0xfc05c000
126 #define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070)
127 #define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500)
129 #define ATMEL_BASE_PIOD 0xfc068000
130 #define ATMEL_BASE_RSTC 0xfc068600
131 #define ATMEL_BASE_PIT 0xfc068630
132 #define ATMEL_BASE_WDT 0xfc068640
134 #define ATMEL_BASE_DBGU 0xfc069000
135 #define ATMEL_BASE_PIOA 0xfc06a000
136 #define ATMEL_BASE_PIOB 0xfc06b000
137 #define ATMEL_BASE_PIOC 0xfc06c000
138 #define ATMEL_BASE_PIOE 0xfc06d000
139 #define ATMEL_BASE_AIC 0xfc06e000
141 #define ATMEL_CHIPID_CIDR 0xfc069040
142 #define ATMEL_CHIPID_EXID 0xfc069044
147 #define ATMEL_BASE_ROM 0x00000000 /* Internal ROM base address */
148 #define ATMEL_BASE_NFC 0x00100000 /* NFC SRAM */
149 #define ATMEL_BASE_SRAM 0x00200000 /* Internal ROM base address */
150 #define ATMEL_BASE_VDEC 0x00300000 /* Video Decoder Controller */
151 #define ATMEL_BASE_UDPHS_FIFO 0x00400000 /* USB Device HS controller */
152 #define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller (OHCI) */
153 #define ATMEL_BASE_EHCI 0x00600000 /* USB Host controller (EHCI) */
154 #define ATMEL_BASE_AXI 0x00700000
155 #define ATMEL_BASE_DAP 0x00800000
156 #define ATMEL_BASE_SMD 0x00900000
161 #define ATMEL_BASE_CS0 0x10000000
162 #define ATMEL_BASE_DDRCS 0x20000000
163 #define ATMEL_BASE_CS1 0x60000000
164 #define ATMEL_BASE_CS2 0x70000000
165 #define ATMEL_BASE_CS3 0x80000000
175 #define H64MX_SLAVE_AXIMX_BRIDGE 0 /* Bridge from H64MX to AXIMX */
190 #define H32MX_SLAVE_H64MX_BRIDGE 0 /* Bridge from H32MX to H64MX */
191 #define H32MX_SLAVE_PERIPH_BRIDGE0 1 /* H32MX Peripheral Bridge 0 */
200 #define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
203 #define ARCH_ID_SAMA5D4 0x8a5c07c0
204 #define ARCH_EXID_SAMA5D41 0x00000001
205 #define ARCH_EXID_SAMA5D42 0x00000002
206 #define ARCH_EXID_SAMA5D43 0x00000003
207 #define ARCH_EXID_SAMA5D44 0x00000004
220 #define CONFIG_SYS_TIMER_COUNTER 0xfc06863c