include/mach/sama5d2.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Chip-specific header file for the SAMA5D2 SoC
13  * Peripheral identifiers/interrupts.
21 #define ATMEL_ID_XDMAC0		6	/* DMA Controller 0 */
22 #define ATMEL_ID_XDMAC1		7	/* DMA Controller 1 */
28 #define ATMEL_ID_MPDDRC		13	/* MPDDR Controller */
29 #define ATMEL_ID_MATRIX1	14	/* H32MX, 32-bit AHB Matrix */
30 #define ATMEL_ID_MATRIX0	15	/* H64MX, 64-bit AHB Matrix */
32 #define ATMEL_ID_HSMC		17	/* Multi-bit ECC interrupt */
33 #define ATMEL_ID_PIOA		18	/* Parallel I/O Controller A */
44 #define ATMEL_ID_TWIHS0		29	/* Two-wire Interface 0 */
45 #define ATMEL_ID_TWIHS1		30	/* Two-wire Interface 1 */
46 #define ATMEL_ID_SDMMC0		31	/* Secure Data Memory Card Controller 0 */
47 #define ATMEL_ID_SDMMC1		32	/* Secure Data Memory Card Controller 1 */
48 #define ATMEL_ID_SPI0		33	/* Serial Peripheral Interface 0 */
49 #define ATMEL_ID_SPI1		34	/* Serial Peripheral Interface 1 */
55 #define ATMEL_ID_ADC		40	/* Touch Screen ADC Controller */
58 #define ATMEL_ID_SSC0		43	/* Serial Synchronous Controller 0 */
59 #define ATMEL_ID_SSC1		44	/* Serial Synchronous Controller 1 */
60 #define ATMEL_ID_LCDC		45	/* LCD Controller */
61 #define ATMEL_ID_ISI		46	/* Image Sensor Controller, for A5D2, named after ISC */
63 #define ATMEL_ID_PDMIC		48	/* PDM Interface Controller */
65 #define ATMEL_ID_SFC		50	/* Fuse Controller */
69 #define ATMEL_ID_I2SC0		54	/* Inter-IC Sound Controller 0 */
70 #define ATMEL_ID_I2SC1		55	/* Inter-IC Sound Controller 1 */
77 #define ATMEL_ID_AIC		62	/* Advanced Interrupt Controller */
78 #define ATMEL_ID_L2CC		63	/* L2 Cache Controller */
83 #define ATMEL_ID_PIOB		68	/* Parallel I/O Controller B */
84 #define ATMEL_ID_PIOC		69	/* Parallel I/O Controller C */
85 #define ATMEL_ID_PIOD		70	/* Parallel I/O Controller D */
86 #define ATMEL_ID_SDMMC0_TIMER	71	/* Secure Data Memory Card Controller 0 (TIMER) */
87 #define ATMEL_ID_SDMMC1_TIMER	72	/* Secure Data Memory Card Controller 1 (TIMER) */
89 #define ATMEL_ID_SYS		74	/* System Controller Interrupt */
91 #define ATMEL_ID_RXLP		76	/* UART Low-Power */
147 #define ATMEL_BASE_UDPHS_FIFO	0x00300000	/* USB Device HS controller */
148 #define ATMEL_BASE_OHCI		0x00400000	/* USB Host controller (OHCI) */
149 #define ATMEL_BASE_EHCI		0x00500000	/* USB Host controller (EHCI) */
181 #define H64MX_SLAVE_PERIPH_BRIDGE	1	/* H64MX Peripheral Bridge */
182 #define H64MX_SLAVE_DDRC_PORT0		2	/* DDR2 Port0-AESOTF */
198 #define H32MX_SLAVE_PERIPH_BRIDGE0	1	/* H32MX Peripheral Bridge 0 */
199 #define H32MX_SLAVE_PERIPH_BRIDGE1	2	/* H32MX Peripheral Bridge 1 */