Lines Matching refs:u32
14 u32 mr;
15 u32 rtr;
16 u32 cr;
17 u32 tpr0;
18 u32 tpr1;
19 u32 tpr2;
20 u32 md;
28 u32 mr; /* 0x00: Mode Register */
29 u32 rtr; /* 0x04: Refresh Timer Register */
30 u32 cr; /* 0x08: Configuration Register */
31 u32 tpr0; /* 0x0c: Timing Parameter 0 Register */
32 u32 tpr1; /* 0x10: Timing Parameter 1 Register */
33 u32 tpr2; /* 0x14: Timing Parameter 2 Register */
34 u32 reserved; /* 0x18: Reserved */
35 u32 lpr; /* 0x1c: Low-power Register */
36 u32 md; /* 0x20: Memory Device Register */
37 u32 reserved1; /* 0x24: Reserved */
38 u32 lpddr23_lpr; /* 0x28: LPDDR2-LPDDR3 Low-power Register*/
39 u32 cal_mr4; /* 0x2c: Calibration and MR4 Register */
40 u32 tim_cal; /* 0x30: Timing Calibration Register */
41 u32 io_calibr; /* 0x34: IO Calibration */
42 u32 ocms; /* 0x38: OCMS Register */
43 u32 ocms_key1; /* 0x3c: OCMS KEY1 Register */
44 u32 ocms_key2; /* 0x40: OCMS KEY2 Register */
45 u32 conf_arbiter; /* 0x44: Configuration Arbiter Register */
46 u32 timeout; /* 0x48: Timeout Port 0/1/2/3 Register */
47 u32 req_port0123; /* 0x4c: Request Port 0/1/2/3 Register */
48 u32 req_port4567; /* 0x50: Request Port 4/5/6/7 Register */
49 u32 bdw_port0123; /* 0x54: Bandwidth Port 0/1/2/3 Register */
50 u32 bdw_port4567; /* 0x58: Bandwidth Port 4/5/6/7 Register */
51 u32 rd_data_path; /* 0x5c: Read Datapath Register */
52 u32 reserved2[33];
53 u32 wpmr; /* 0xe4: Write Protection Mode Register */
54 u32 wpsr; /* 0xe8: Write Protection Status Register */
55 u32 reserved3[4];
56 u32 version; /* 0xfc: IP version */