Lines Matching +full:0 +full:x7f

22 #define AT91_ASM_SMC_PULSE0	(ATMEL_BASE_SMC + 0x04)
23 #define AT91_ASM_SMC_CYCLE0	(ATMEL_BASE_SMC + 0x08)
24 #define AT91_ASM_SMC_MODE0	(ATMEL_BASE_SMC + 0x0C)
29 	u32	setup;		/* 0x00 SMC Setup Register */
30 	u32	pulse;		/* 0x04 SMC Pulse Register */
31 	u32	cycle;		/* 0x08 SMC Cycle Register */
32 	u32	mode;		/* 0x0C SMC Mode Register */
41 #define AT91_SMC_SETUP_NWE(x)		(x & 0x3f)
42 #define AT91_SMC_SETUP_NCS_WR(x)	((x & 0x3f) << 8)
43 #define AT91_SMC_SETUP_NRD(x)		((x & 0x3f) << 16)
44 #define AT91_SMC_SETUP_NCS_RD(x)	((x & 0x3f) << 24)
46 #define AT91_SMC_PULSE_NWE(x)		(x & 0x7f)
47 #define AT91_SMC_PULSE_NCS_WR(x)	((x & 0x7f) << 8)
48 #define AT91_SMC_PULSE_NRD(x)		((x & 0x7f) << 16)
49 #define AT91_SMC_PULSE_NCS_RD(x)	((x & 0x7f) << 24)
51 #define AT91_SMC_CYCLE_NWE(x)		(x & 0x1ff)
52 #define AT91_SMC_CYCLE_NRD(x)		((x & 0x1ff) << 16)
54 #define AT91_SMC_MODE_RM_NCS		0x00000000
55 #define AT91_SMC_MODE_RM_NRD		0x00000001
56 #define AT91_SMC_MODE_WM_NCS		0x00000000
57 #define AT91_SMC_MODE_WM_NWE		0x00000002
59 #define AT91_SMC_MODE_EXNW_DISABLE	0x00000000
60 #define AT91_SMC_MODE_EXNW_FROZEN	0x00000020
61 #define AT91_SMC_MODE_EXNW_READY	0x00000030
63 #define AT91_SMC_MODE_BAT		0x00000100
64 #define AT91_SMC_MODE_DBW_8		0x00000000
65 #define AT91_SMC_MODE_DBW_16		0x00001000
66 #define AT91_SMC_MODE_DBW_32		0x00002000
67 #define AT91_SMC_MODE_TDF_CYCLE(x)	((x & 0xf) << 16)
68 #define AT91_SMC_MODE_TDF		0x00100000
69 #define AT91_SMC_MODE_PMEN		0x01000000
70 #define AT91_SMC_MODE_PS_4		0x00000000
71 #define AT91_SMC_MODE_PS_8		0x10000000
72 #define AT91_SMC_MODE_PS_16		0x20000000
73 #define AT91_SMC_MODE_PS_32		0x30000000