Lines Matching full:master

63 	u32		mrcr;		/* 0x100 Master Remap Control */
100 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
102 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
121 /* Default Master Type */
126 /* Fixed Index of Default Master */
148 /* Master Remap Control Register */
151 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
153 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
227 #define AT91_MATRIX_PRA_M0(x)	((x & 3) << 0)	/* Master 0 Priority Reg. A*/
228 #define AT91_MATRIX_PRA_M1(x)	((x & 3) << 4)	/* Master 1 Priority Reg. A*/
229 #define AT91_MATRIX_PRA_M2(x)	((x & 3) << 8)	/* Master 2 Priority Reg. A*/
230 #define AT91_MATRIX_PRA_M3(x)	((x & 3) << 12)	/* Master 3 Priority Reg. A*/
231 #define AT91_MATRIX_PRA_M4(x)	((x & 3) << 16)	/* Master 4 Priority Reg. A*/
232 #define AT91_MATRIX_PRA_M5(x)	((x & 3) << 20)	/* Master 5 Priority Reg. A*/
233 #define AT91_MATRIX_PRA_M6(x)	((x & 3) << 24)	/* Master 6 Priority Reg. A*/
234 #define AT91_MATRIX_PRA_M7(x)	((x & 3) << 28)	/* Master 7 Priority Reg. A*/
235 #define AT91_MATRIX_PRB_M8(x)	((x & 3) << 0)	/* Master 8 Priority Reg. B) */
236 #define AT91_MATRIX_PRB_M9(x)	((x & 3) << 4)	/* Master 9 Priority Reg. B) */
237 #define AT91_MATRIX_PRB_M10(x)	((x & 3) << 8)	/* Master 10 Priority Reg. B) */