63 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 29, 1);	/* TXD1 */  in at91_serial1_hw_init()
64 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 28, 0);	/* RXD1 */  in at91_serial1_hw_init()
81 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 31, 1);	/* DTXD */  in at91_seriald_hw_init()
82 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 30, 0);	/* DRXD */  in at91_seriald_hw_init()
150 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* GTX0 */  in at91_gmac_hw_init()
151 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* GTX1 */  in at91_gmac_hw_init()
152 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* GTX2 */  in at91_gmac_hw_init()
153 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 3, 0);	/* GTX3 */  in at91_gmac_hw_init()
154 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 4, 0);	/* GRX0 */  in at91_gmac_hw_init()
155 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 5, 0);	/* GRX1 */  in at91_gmac_hw_init()
156 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* GRX2 */  in at91_gmac_hw_init()
157 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* GRX3 */  in at91_gmac_hw_init()
158 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* GTXCK */  in at91_gmac_hw_init()
159 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* GTXEN */  in at91_gmac_hw_init()
161 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 11, 0);	/* GRXCK */  in at91_gmac_hw_init()
162 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* GRXER */  in at91_gmac_hw_init()
164 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* GMDC */  in at91_gmac_hw_init()
165 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* GMDIO */  in at91_gmac_hw_init()
166 	at91_pio3_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* G125CK */  in at91_gmac_hw_init()