Lines Matching refs:u32
28 u32 pl310_cache_id;
29 u32 pl310_cache_type;
30 u32 pad1[62];
31 u32 pl310_ctrl;
32 u32 pl310_aux_ctrl;
33 u32 pl310_tag_latency_ctrl;
34 u32 pl310_data_latency_ctrl;
35 u32 pad2[60];
36 u32 pl310_event_cnt_ctrl;
37 u32 pl310_event_cnt1_cfg;
38 u32 pl310_event_cnt0_cfg;
39 u32 pl310_event_cnt1_val;
40 u32 pl310_event_cnt0_val;
41 u32 pl310_intr_mask;
42 u32 pl310_masked_intr_stat;
43 u32 pl310_raw_intr_stat;
44 u32 pl310_intr_clear;
45 u32 pad3[323];
46 u32 pl310_cache_sync;
47 u32 pad4[15];
48 u32 pl310_inv_line_pa;
49 u32 pad5[2];
50 u32 pl310_inv_way;
51 u32 pad6[12];
52 u32 pl310_clean_line_pa;
53 u32 pad7[1];
54 u32 pl310_clean_line_idx;
55 u32 pl310_clean_way;
56 u32 pad8[12];
57 u32 pl310_clean_inv_line_pa;
58 u32 pad9[1];
59 u32 pl310_clean_inv_line_idx;
60 u32 pl310_clean_inv_way;
61 u32 pad10[64];
62 u32 pl310_lockdown_dbase;
63 u32 pl310_lockdown_ibase;
64 u32 pad11[190];
65 u32 pl310_addr_filter_start;
66 u32 pl310_addr_filter_end;
67 u32 pad12[190];
68 u32 pl310_test_operation;
69 u32 pad13[3];
70 u32 pl310_line_data;
71 u32 pad14[7];
72 u32 pl310_line_tag;
73 u32 pad15[3];
74 u32 pl310_debug_ctrl;
75 u32 pad16[7];
76 u32 pl310_prefetch_ctrl;
77 u32 pad17[7];
78 u32 pl310_power_ctrl;
83 void pl310_inval_range(u32 start, u32 end);
84 void pl310_clean_inval_range(u32 start, u32 end);