Lines Matching defs:prcm_regs
17 struct prcm_regs { struct
19 u32 cm_clksel_core;
20 u32 cm_clksel_abe;
21 u32 cm_dll_ctrl;
22 u32 cm_clkmode_dpll_core;
23 u32 cm_idlest_dpll_core;
24 u32 cm_autoidle_dpll_core;
25 u32 cm_clksel_dpll_core;
26 u32 cm_div_m2_dpll_core;
27 u32 cm_div_m3_dpll_core;
28 u32 cm_div_h11_dpll_core;
29 u32 cm_div_h12_dpll_core;
30 u32 cm_div_h13_dpll_core;
31 u32 cm_div_h14_dpll_core;
32 u32 cm_div_h21_dpll_core;
33 u32 cm_div_h24_dpll_core;
34 u32 cm_ssc_deltamstep_dpll_core;
35 u32 cm_ssc_modfreqdiv_dpll_core;
36 u32 cm_emu_override_dpll_core;
37 u32 cm_div_h22_dpllcore;
38 u32 cm_div_h23_dpll_core;
39 u32 cm_clkmode_dpll_mpu;
40 u32 cm_idlest_dpll_mpu;
41 u32 cm_autoidle_dpll_mpu;
42 u32 cm_clksel_dpll_mpu;
43 u32 cm_div_m2_dpll_mpu;
44 u32 cm_ssc_deltamstep_dpll_mpu;
45 u32 cm_ssc_modfreqdiv_dpll_mpu;
46 u32 cm_bypclk_dpll_mpu;
47 u32 cm_clkmode_dpll_iva;
48 u32 cm_idlest_dpll_iva;
49 u32 cm_autoidle_dpll_iva;
50 u32 cm_clksel_dpll_iva;
51 u32 cm_div_h11_dpll_iva;
52 u32 cm_div_h12_dpll_iva;
53 u32 cm_ssc_deltamstep_dpll_iva;
54 u32 cm_ssc_modfreqdiv_dpll_iva;
55 u32 cm_bypclk_dpll_iva;
56 u32 cm_clkmode_dpll_abe;
57 u32 cm_idlest_dpll_abe;
58 u32 cm_autoidle_dpll_abe;
59 u32 cm_clksel_dpll_abe;
60 u32 cm_div_m2_dpll_abe;
61 u32 cm_div_m3_dpll_abe;
62 u32 cm_ssc_deltamstep_dpll_abe;
63 u32 cm_ssc_modfreqdiv_dpll_abe;
64 u32 cm_clkmode_dpll_ddrphy;
65 u32 cm_idlest_dpll_ddrphy;
66 u32 cm_autoidle_dpll_ddrphy;
67 u32 cm_clksel_dpll_ddrphy;
68 u32 cm_div_m2_dpll_ddrphy;
69 u32 cm_div_h11_dpll_ddrphy;
70 u32 cm_div_h12_dpll_ddrphy;
71 u32 cm_div_h13_dpll_ddrphy;
72 u32 cm_ssc_deltamstep_dpll_ddrphy;
73 u32 cm_clkmode_dpll_dsp;
74 u32 cm_shadow_freq_config1;
75 u32 cm_clkmode_dpll_gmac;
76 u32 cm_mpu_mpu_clkctrl;
79 u32 cm_dsp_clkstctrl;
80 u32 cm_dsp_dsp_clkctrl;
83 u32 cm1_abe_clkstctrl;
84 u32 cm1_abe_l4abe_clkctrl;
85 u32 cm1_abe_aess_clkctrl;
86 u32 cm1_abe_pdm_clkctrl;
87 u32 cm1_abe_dmic_clkctrl;
88 u32 cm1_abe_mcasp_clkctrl;
89 u32 cm1_abe_mcbsp1_clkctrl;
90 u32 cm1_abe_mcbsp2_clkctrl;
91 u32 cm1_abe_mcbsp3_clkctrl;
92 u32 cm1_abe_slimbus_clkctrl;
93 u32 cm1_abe_timer5_clkctrl;
94 u32 cm1_abe_timer6_clkctrl;
95 u32 cm1_abe_timer7_clkctrl;
96 u32 cm1_abe_timer8_clkctrl;
97 u32 cm1_abe_wdt3_clkctrl;
100 u32 cm_clksel_mpu_m3_iss_root;
101 u32 cm_clksel_usb_60mhz;
102 u32 cm_scale_fclk;
103 u32 cm_core_dvfs_perf1;
104 u32 cm_core_dvfs_perf2;
105 u32 cm_core_dvfs_perf3;
106 u32 cm_core_dvfs_perf4;
107 u32 cm_core_dvfs_current;
108 u32 cm_iva_dvfs_perf_tesla;
109 u32 cm_iva_dvfs_perf_ivahd;
110 u32 cm_iva_dvfs_perf_abe;
111 u32 cm_iva_dvfs_current;
112 u32 cm_clkmode_dpll_per;
113 u32 cm_idlest_dpll_per;
114 u32 cm_autoidle_dpll_per;
115 u32 cm_clksel_dpll_per;
116 u32 cm_div_m2_dpll_per;
117 u32 cm_div_m3_dpll_per;
118 u32 cm_div_h11_dpll_per;
119 u32 cm_div_h12_dpll_per;
120 u32 cm_div_h13_dpll_per;
121 u32 cm_div_h14_dpll_per;
122 u32 cm_ssc_deltamstep_dpll_per;
123 u32 cm_ssc_modfreqdiv_dpll_per;
124 u32 cm_emu_override_dpll_per;
125 u32 cm_clkmode_dpll_usb;
126 u32 cm_idlest_dpll_usb;
127 u32 cm_autoidle_dpll_usb;
128 u32 cm_clksel_dpll_usb;
129 u32 cm_div_m2_dpll_usb;
130 u32 cm_ssc_deltamstep_dpll_usb;
131 u32 cm_ssc_modfreqdiv_dpll_usb;
132 u32 cm_clkdcoldo_dpll_usb;
133 u32 cm_clkmode_dpll_pcie_ref;
134 u32 cm_clkmode_apll_pcie;
135 u32 cm_idlest_apll_pcie;
136 u32 cm_div_m2_apll_pcie;
137 u32 cm_clkvcoldo_apll_pcie;
138 u32 cm_clkmode_dpll_unipro;
139 u32 cm_idlest_dpll_unipro;
140 u32 cm_autoidle_dpll_unipro;
141 u32 cm_clksel_dpll_unipro;
142 u32 cm_div_m2_dpll_unipro;
143 u32 cm_ssc_deltamstep_dpll_unipro;
144 u32 cm_ssc_modfreqdiv_dpll_unipro;
145 u32 cm_coreaon_usb_phy1_core_clkctrl;
146 u32 cm_coreaon_usb_phy2_core_clkctrl;
147 u32 cm_coreaon_usb_phy3_core_clkctrl;
148 u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
151 u32 cm_coreaon_bandgap_clkctrl;
152 u32 cm_coreaon_io_srcomp_clkctrl;
153 u32 cm_l3_1_clkstctrl;
154 u32 cm_l3_1_dynamicdep;
155 u32 cm_l3_1_l3_1_clkctrl;
156 u32 cm_l3_2_clkstctrl;
157 u32 cm_l3_2_dynamicdep;
158 u32 cm_l3_2_l3_2_clkctrl;
159 u32 cm_l3_gpmc_clkctrl;
160 u32 cm_l3_2_ocmc_ram_clkctrl;
161 u32 cm_mpu_m3_clkstctrl;
162 u32 cm_mpu_m3_staticdep;
163 u32 cm_mpu_m3_dynamicdep;
164 u32 cm_mpu_m3_mpu_m3_clkctrl;
165 u32 cm_sdma_clkstctrl;
166 u32 cm_sdma_staticdep;
167 u32 cm_sdma_dynamicdep;
168 u32 cm_sdma_sdma_clkctrl;
169 u32 cm_memif_clkstctrl;
170 u32 cm_memif_dmm_clkctrl;
171 u32 cm_memif_emif_fw_clkctrl;
172 u32 cm_memif_emif_1_clkctrl;
173 u32 cm_memif_emif_2_clkctrl;
174 u32 cm_memif_dll_clkctrl;
175 u32 cm_memif_emif_h1_clkctrl;
176 u32 cm_memif_emif_h2_clkctrl;
177 u32 cm_memif_dll_h_clkctrl;
178 u32 cm_c2c_clkstctrl;
179 u32 cm_c2c_staticdep;
180 u32 cm_c2c_dynamicdep;
181 u32 cm_c2c_sad2d_clkctrl;
182 u32 cm_c2c_modem_icr_clkctrl;
183 u32 cm_c2c_sad2d_fw_clkctrl;
184 u32 cm_l4cfg_clkstctrl;
185 u32 cm_l4cfg_dynamicdep;
186 u32 cm_l4cfg_l4_cfg_clkctrl;
187 u32 cm_l4cfg_hw_sem_clkctrl;
188 u32 cm_l4cfg_mailbox_clkctrl;
189 u32 cm_l4cfg_sar_rom_clkctrl;
190 u32 cm_l3instr_clkstctrl;
191 u32 cm_l3instr_l3_3_clkctrl;
192 u32 cm_l3instr_l3_instr_clkctrl;
193 u32 cm_l3instr_intrconn_wp1_clkctrl;
196 u32 cm_ivahd_clkstctrl;
197 u32 cm_ivahd_ivahd_clkctrl;
198 u32 cm_ivahd_sl2_clkctrl;
201 u32 cm_cam_clkstctrl;
202 u32 cm_cam_iss_clkctrl;
203 u32 cm_cam_fdif_clkctrl;
204 u32 cm_cam_vip1_clkctrl;
205 u32 cm_cam_vip2_clkctrl;
206 u32 cm_cam_vip3_clkctrl;
207 u32 cm_cam_lvdsrx_clkctrl;
208 u32 cm_cam_csi1_clkctrl;
209 u32 cm_cam_csi2_clkctrl;
212 u32 cm_dss_clkstctrl;
213 u32 cm_dss_dss_clkctrl;
216 u32 cm_sgx_clkstctrl;
217 u32 cm_sgx_sgx_clkctrl;
220 u32 cm_l3init_clkstctrl;
223 u32 cm_l3init_hsmmc1_clkctrl;
224 u32 cm_l3init_hsmmc2_clkctrl;
225 u32 cm_l3init_hsi_clkctrl;
226 u32 cm_l3init_hsusbhost_clkctrl;
227 u32 cm_l3init_hsusbotg_clkctrl;
228 u32 cm_l3init_hsusbtll_clkctrl;
229 u32 cm_l3init_p1500_clkctrl;
230 u32 cm_l3init_sata_clkctrl;
231 u32 cm_l3init_fsusb_clkctrl;
232 u32 cm_l3init_ocp2scp1_clkctrl;
233 u32 cm_l3init_ocp2scp3_clkctrl;
234 u32 cm_l3init_usb_otg_ss1_clkctrl;
235 u32 cm_l3init_usb_otg_ss2_clkctrl;
237 u32 prm_irqstatus_mpu;
238 u32 prm_irqstatus_mpu_2;
241 u32 cm_l4per_clkstctrl;
242 u32 cm_l4per_dynamicdep;
243 u32 cm_l4per_adc_clkctrl;
244 u32 cm_l4per_gptimer10_clkctrl;
245 u32 cm_l4per_gptimer11_clkctrl;
246 u32 cm_l4per_gptimer2_clkctrl;
247 u32 cm_l4per_gptimer3_clkctrl;
248 u32 cm_l4per_gptimer4_clkctrl;
249 u32 cm_l4per_gptimer9_clkctrl;
250 u32 cm_l4per_elm_clkctrl;
251 u32 cm_l4per_gpio2_clkctrl;
252 u32 cm_l4per_gpio3_clkctrl;
253 u32 cm_l4per_gpio4_clkctrl;
254 u32 cm_l4per_gpio5_clkctrl;
255 u32 cm_l4per_gpio6_clkctrl;
256 u32 cm_l4per_hdq1w_clkctrl;
257 u32 cm_l4per_hecc1_clkctrl;
258 u32 cm_l4per_hecc2_clkctrl;
259 u32 cm_l4per_i2c1_clkctrl;
260 u32 cm_l4per_i2c2_clkctrl;
261 u32 cm_l4per_i2c3_clkctrl;
262 u32 cm_l4per_i2c4_clkctrl;
263 u32 cm_l4per_l4per_clkctrl;
264 u32 cm_l4per_mcasp2_clkctrl;
265 u32 cm_l4per_mcasp3_clkctrl;
266 u32 cm_l4per_mgate_clkctrl;
267 u32 cm_l4per_mcspi1_clkctrl;
268 u32 cm_l4per_mcspi2_clkctrl;
269 u32 cm_l4per_mcspi3_clkctrl;
270 u32 cm_l4per_mcspi4_clkctrl;
271 u32 cm_l4per_gpio7_clkctrl;
272 u32 cm_l4per_gpio8_clkctrl;
273 u32 cm_l4per_mmcsd3_clkctrl;
274 u32 cm_l4per_mmcsd4_clkctrl;
275 u32 cm_l4per_msprohg_clkctrl;
276 u32 cm_l4per_slimbus2_clkctrl;
277 u32 cm_l4per_qspi_clkctrl;
278 u32 cm_l4per_uart1_clkctrl;
279 u32 cm_l4per_uart2_clkctrl;
280 u32 cm_l4per_uart3_clkctrl;
281 u32 cm_l4per_uart4_clkctrl;
282 u32 cm_l4per_mmcsd5_clkctrl;
283 u32 cm_l4per_i2c5_clkctrl;
284 u32 cm_l4per_uart5_clkctrl;
285 u32 cm_l4per_uart6_clkctrl;
286 u32 cm_l4sec_clkstctrl;
287 u32 cm_l4sec_staticdep;
288 u32 cm_l4sec_dynamicdep;
289 u32 cm_l4sec_aes1_clkctrl;
290 u32 cm_l4sec_aes2_clkctrl;
291 u32 cm_l4sec_des3des_clkctrl;
292 u32 cm_l4sec_pkaeip29_clkctrl;
293 u32 cm_l4sec_rng_clkctrl;
294 u32 cm_l4sec_sha2md51_clkctrl;
295 u32 cm_l4sec_cryptodma_clkctrl;
298 u32 cm_abe_pll_ref_clksel;
299 u32 cm_sys_clksel;
300 u32 cm_abe_pll_sys_clksel;
301 u32 cm_wkup_clkstctrl;
302 u32 cm_wkup_l4wkup_clkctrl;
303 u32 cm_wkup_wdtimer1_clkctrl;
304 u32 cm_wkup_wdtimer2_clkctrl;
305 u32 cm_wkup_gpio1_clkctrl;
306 u32 cm_wkup_gptimer1_clkctrl;
307 u32 cm_wkup_gptimer12_clkctrl;
308 u32 cm_wkup_synctimer_clkctrl;
309 u32 cm_wkup_usim_clkctrl;
310 u32 cm_wkup_sarram_clkctrl;
311 u32 cm_wkup_keyboard_clkctrl;
312 u32 cm_wkup_rtc_clkctrl;
313 u32 cm_wkup_bandgap_clkctrl;
314 u32 cm_wkupaon_scrm_clkctrl;
315 u32 cm_wkupaon_io_srcomp_clkctrl;
316 u32 prm_rstctrl;
317 u32 prm_rstst;
318 u32 prm_rsttime;
319 u32 prm_io_pmctrl;
320 u32 prm_vc_val_bypass;
321 u32 prm_vc_cfg_i2c_mode;
322 u32 prm_vc_cfg_i2c_clk;
323 u32 prm_abbldo_mpu_setup;
324 u32 prm_abbldo_mpu_ctrl;
325 u32 prm_abbldo_mm_setup;
326 u32 prm_abbldo_mm_ctrl;
327 u32 prm_abbldo_iva_setup;
328 u32 prm_abbldo_iva_ctrl;
329 u32 prm_abbldo_eve_setup;
330 u32 prm_abbldo_eve_ctrl;
331 u32 prm_abbldo_gpu_setup;
332 u32 prm_abbldo_gpu_ctrl;
334 u32 cm_div_m4_dpll_core;
335 u32 cm_div_m5_dpll_core;
336 u32 cm_div_m6_dpll_core;
337 u32 cm_div_m7_dpll_core;
338 u32 cm_div_m4_dpll_iva;
339 u32 cm_div_m5_dpll_iva;
340 u32 cm_div_m4_dpll_ddrphy;
341 u32 cm_div_m5_dpll_ddrphy;
342 u32 cm_div_m6_dpll_ddrphy;
343 u32 cm_div_m4_dpll_per;
344 u32 cm_div_m5_dpll_per;
345 u32 cm_div_m6_dpll_per;
346 u32 cm_div_m7_dpll_per;
347 u32 cm_l3instr_intrconn_wp1_clkct;
348 u32 cm_l3init_usbphy_clkctrl;
349 u32 cm_l4per_mcbsp4_clkctrl;
350 u32 prm_vc_cfg_channel;
353 u32 scrm_auxclk0;
354 u32 scrm_auxclk1;
357 u32 cm_gmac_gmac_clkctrl;
358 u32 cm_gmac_clkstctrl;
361 u32 cm_ipu_clkstctrl;
362 u32 cm_ipu_i2c5_clkctrl;
365 u32 cm_l3main1_tptc1_clkctrl;
366 u32 cm_l3main1_tptc2_clkctrl;