Lines Matching +full:emc +full:- +full:cfg +full:- +full:2

1 /* SPDX-License-Identifier: GPL-2.0+ */
14 /* EMC Registers */
16 	u32 cfg;		/* 0x00: EMC_CFG */  member
20 	u32 reserved1[2];	/* 0x18 ~ 0x18 */
78  * Set up the EMC for the given rate. The timing parameters are retrieved
79  * from the device tree "nvidia,tegra20-emc" node and its
80  * "nvidia,tegra20-emc-table" sub-nodes.
83  * @param rate	Clock speed of memory controller in Hz (=2x memory bus rate)
84  * @return 0 if ok, else -ve error code (look in emc.c to decode it)
89  * Get a pointer to the EMC controller from the device tree.
92  * @return pointer to EMC controller