Lines Matching +full:0 +full:x170
12 /* 0x000 */
18 /* 0x010 */
23 /* 0x020 */
26 /* 0x100 */
33 /* 0x120 */
39 /* 0x130 */
42 /* 0x140 */
48 /* 0x150 */
54 /* 0x160 */
60 /* 0x170 */
66 /* 0x180 */
71 /* 0x1a0 */
77 /* 0x1b0 */
80 /* 0x200 */
81 uint reserved11[0x80];
83 /* 0x130 */
89 /* 0x140 */
95 /* 0x150 */
101 /* 0x160 */
105 /* 0x170 */
110 /* 0x190 */
113 /* 0x1b0 */
118 /* 0x1c0 */
121 /* 0x1d0 */
124 /* 0x1e0 */
127 /* 0x1f0 */
133 /* 0x200 */
137 uint reserved11_1[0x7D];
140 /* 0x400 */
147 /* 0x410 */
151 /* 0x424 */
157 /* 0x410 */
161 /* 0x420 */
165 /* 0x500 */
168 /* 0x800 */
174 /* 0x810 */
180 /* 0x820 */
186 /* 0x830 */
198 #define VBUS_SENSE_CTL_VBUS_WAKEUP 0
218 #define ULPI_DATA_TRIMMER_LOAD (1 << 0)
219 #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
221 #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
223 #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
238 (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
245 (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
251 (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
252 #define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
253 #define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
261 (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
262 #define UTMIP_HSSQUELCH_LEVEL_SHIFT 0
264 (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
270 (0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
273 (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
276 #define UTMIP_DEBOUNCE_CFG0_SHIFT 0
277 #define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
290 #define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
293 (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
298 (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
316 #define PTS_MASK (0x7U << PTS_SHIFT)
320 #define PTS_UTMI 0
338 (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
340 #define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
341 #define UTMIP_XCVR_SETUP_SHIFT 0
342 #define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
347 (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
348 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)