Lines Matching full:enum
12 enum clock_osc_freq {
33 enum {
44 enum clock_osc_freq clock_get_osc_freq(void);
61 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
73 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
88 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
96 void clock_enable(enum periph_id clkid);
103 void clock_disable(enum periph_id clkid);
111 void clock_set_enable(enum periph_id clkid, int enable);
120 void reset_periph(enum periph_id periph_id, int us_delay);
128 void reset_set_enable(enum periph_id periph_id, int enable);
132 enum crc_reset_id {
160 void clock_ll_set_source(enum periph_id periph_id, unsigned source);
170 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
185 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
196 enum clock_id clock_get_periph_parent(enum periph_id periph_id);
207 unsigned clock_start_periph_pll(enum periph_id periph_id,
208 enum clock_id parent, unsigned rate);
220 unsigned long clock_get_periph_rate(enum periph_id periph_id,
221 enum clock_id parent);
236 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
237 enum clock_id parent, unsigned rate, int *extra_div);
245 unsigned clock_get_rate(enum clock_id clkid);
256 void clock_ll_start_uart(enum periph_id periph_id);
294 u32 *get_periph_source_reg(enum periph_id periph_id);
297 struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid);
313 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
327 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source);
341 int get_periph_clock_source(enum periph_id periph_id,
342 enum clock_id parent, int *mux_bits, int *divider_bits);
352 enum periph_id clk_id_to_periph_id(int clk_id);
371 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
408 enum periph_id periph_id;
409 enum clock_id parent_clock_id;