Lines Matching refs:u32
16 u32 gctrl; /* 0x00 global control */
17 u32 clkcr; /* 0x04 clock control */
18 u32 timeout; /* 0x08 time out */
19 u32 width; /* 0x0c bus width */
20 u32 blksz; /* 0x10 block size */
21 u32 bytecnt; /* 0x14 byte count */
22 u32 cmd; /* 0x18 command */
23 u32 arg; /* 0x1c argument */
24 u32 resp0; /* 0x20 response 0 */
25 u32 resp1; /* 0x24 response 1 */
26 u32 resp2; /* 0x28 response 2 */
27 u32 resp3; /* 0x2c response 3 */
28 u32 imask; /* 0x30 interrupt mask */
29 u32 mint; /* 0x34 masked interrupt status */
30 u32 rint; /* 0x38 raw interrupt status */
31 u32 status; /* 0x3c status */
32 u32 ftrglevel; /* 0x40 FIFO threshold watermark*/
33 u32 funcsel; /* 0x44 function select */
34 u32 cbcr; /* 0x48 CIU byte count */
35 u32 bbcr; /* 0x4c BIU byte count */
36 u32 dbgc; /* 0x50 debug enable */
37 u32 res0; /* 0x54 reserved */
38 u32 a12a; /* 0x58 Auto command 12 argument */
39 u32 ntsr; /* 0x5c New timing set register */
40 u32 res1[8];
41 u32 dmac; /* 0x80 internal DMA control */
42 u32 dlba; /* 0x84 internal DMA descr list base address */
43 u32 idst; /* 0x88 internal DMA status */
44 u32 idie; /* 0x8c internal DMA interrupt enable */
45 u32 chda; /* 0x90 */
46 u32 cbda; /* 0x94 */
47 u32 res2[26];
49 u32 res3[17];
50 u32 samp_dl;
51 u32 res4[46];
53 u32 fifo; /* 0x100 / 0x200 FIFO access address */