182 #define MCTL_INIT0_POST_CKE_x1024(n)    ((n & 0x0fff) << 16)  argument
187 #define MCTL_INIT0_PRE_CKE_x1024(n)     ((n & 0x0fff) <<  0)  argument
188 #define MCTL_INIT1_DRAM_RSTN_x1024(n)   ((n & 0xff) << 16)  argument
189 #define MCTL_INIT1_FINAL_WAIT_x32(n)    ((n & 0x3f) <<  8)  argument
190 #define MCTL_INIT1_PRE_OCD_x32(n)       ((n & 0x0f) <<  0)  argument
191 #define MCTL_INIT2_IDLE_AFTER_RESET_x32(n)  ((n & 0xff) << 8)  argument
192 #define MCTL_INIT2_MIN_STABLE_CLOCK_x1(n)   ((n & 0x0f) << 0)  argument
193 #define MCTL_INIT3_MR(n)                ((n & 0xffff) << 16)  argument
194 #define MCTL_INIT3_EMR(n)               ((n & 0xffff) <<  0)  argument
195 #define MCTL_INIT4_EMR2(n)              ((n & 0xffff) << 16)  argument
196 #define MCTL_INIT4_EMR3(n)              ((n & 0xffff) <<  0)  argument
197 #define MCTL_INIT5_DEV_ZQINIT_x32(n)        ((n & 0x00ff) << 16)  argument
198 #define MCTL_INIT5_MAX_AUTO_INIT_x1024(n)   ((n & 0x03ff) <<  0);  argument
241 #define MCTL_DTCR_RANKEN(n)                (((n == 2) ? 3 : 1) << 24)  argument
260 #define DDR3_MR0_WR(n) \  argument
262 #define DDR3_MR0_CL(n) \  argument
268 #define DDR3_MR2_TWL(n) \  argument