Lines Matching refs:REGS_AHB0_BASE
12 #define REGS_AHB0_BASE 0x01C00000 macro
22 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
23 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
25 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
27 #define SUNXI_SID_BASE (REGS_AHB0_BASE + 0xe200)
29 #define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000)
30 #define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000)
31 #define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000)
32 #define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000)
33 #define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000)
35 #define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000)
36 #define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000)
37 #define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000)
38 #define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000)
40 #define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000)
41 #define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000)
42 #define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000)
44 #define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000)
45 #define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000)
46 #define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000)
47 #define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000)
48 #define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000)