Lines Matching full:configuration
12 u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */
13 u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */
14 u32 pll3_audio_cfg; /* 0x08 audio pll configuration */
15 u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */
16 u32 pll5_ve_cfg; /* 0x10 videoengine pll configuration */
17 u32 pll6_ddr_cfg; /* 0x14 ddr pll configuration */
18 u32 pll7_video0_cfg; /* 0x18 video0 pll configuration */
19 u32 pll8_video1_cfg; /* 0x1c video1 pll configuration */
20 u32 pll9_gpu_cfg; /* 0x20 gpu pll configuration */
21 u32 pll10_de_cfg; /* 0x24 displayengine pll configuration */
23 u32 pll12_periph1_cfg; /* 0x2c peripheral1 pll configuration */
25 u32 cpu_clk_source; /* 0x50 cpu clk source configuration */
26 u32 c0_cfg; /* 0x54 cpu cluster 0 clock configuration */
27 u32 c1_cfg; /* 0x58 cpu cluster 1 clock configuration */
28 u32 gtbus_cfg; /* 0x5c gtbus clock configuration */
29 u32 ahb0_cfg; /* 0x60 ahb0 clock configuration */
30 u32 ahb1_cfg; /* 0x64 ahb1 clock configuration */
31 u32 ahb2_cfg; /* 0x68 ahb2 clock configuration */
33 u32 apb0_cfg; /* 0x70 apb0 clock configuration */
34 u32 apb1_cfg; /* 0x74 apb1 clock configuration */
35 u32 cci400_cfg; /* 0x78 cci400 clock configuration */
37 u32 ats_cfg; /* 0x80 ats clock configuration */
38 u32 trace_cfg; /* 0x84 trace clock configuration */
47 u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
49 u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */
50 u32 sd1_clk_cfg; /* 0x414 sd1 clock configuration */
51 u32 sd2_clk_cfg; /* 0x418 sd2 clock configuration */
52 u32 sd3_clk_cfg; /* 0x41c sd3 clock configuration */
56 u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */
57 u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */
58 u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */
59 u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */
63 u32 de_clk_cfg; /* 0x490 display engine clock configuration */
65 u32 mp_clk_cfg; /* 0x498 mp clock configuration */