asm/arch-sunxi/clock_sun6i.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
5  * (C) Copyright 2007-2011
30 	u32 mipi_pll_cfg;	/* 0x40 MIPI pll control */
95 	u32 csi1_clk_cfg;	/* 0x138 CSI1 module clock */
115 	u32 mipi_dsi_clk_cfg;	/* 0x168 MIPI DSI clock control */
116 	u32 mipi_csi_clk_cfg;	/* 0x16c MIPI CSI clock control */
138 	u32 mipi_bias_cfg;	/* 0x240 MIPI Bias config */
152 	u32 mipi_pattern_cfg;	/* 0x2a0 MIPI Pattern config */
181 #define APB2_CLK_RATE_M(m)		(((m)-1) << 0)
206 #define CCM_PLL1_CTRL_M(n)		((((n) - 1) & 0x3) << 0)
207 #define CCM_PLL1_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
208 #define CCM_PLL1_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
214 #define CCM_PLL3_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
217 #define CCM_PLL3_CTRL_N(n)		((((n) - 1) & 0x7f) << 8)
222 #define CCM_PLL5_CTRL_M(n)		((((n) - 1) & 0x3) << 0)
223 #define CCM_PLL5_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
224 #define CCM_PLL5_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
241 #define CCM_MIPI_PLL_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
244 #define CCM_MIPI_PLL_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
247 #define CCM_MIPI_PLL_CTRL_N(n)		((((n) - 1) & 0xf) << 8)
253 #define CCM_PLL10_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
256 #define CCM_PLL10_CTRL_N(n)		((((n) - 1) & 0x7f) << 8)
261 #define CCM_PLL11_CTRL_N(n)		((((n) - 1) & 0x3f) << 8)
283  * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
284  * them 0 - 2 like they were called on older SoCs.
340 #define CCM_NAND_CTRL_M(x)		((x) - 1)
345 #define CCM_MMC_CTRL_M(x)		((x) - 1)
386 #define CCM_DRAMCLK_CFG_DIV(x)		((x - 1) << 0)
388 #define CCM_DRAMCLK_CFG_DIV0(x)		((x - 1) << 8)
417 #define CCM_LCD_CH1_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
426 #define CCM_LCD0_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
429 #define CCM_LCD1_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
431 #define CCM_HDMI_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
443 #define CCM_TVE_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
498 #define CCM_DE_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
509 #define CCM_DE2_CTRL_M(n)		((((n) - 1) & 0xf) << 0)