Lines Matching defs:mscm_ir
274 struct mscm_ir { struct
275 u32 cpxtype; /* Processor x Type Register */
276 u32 cpxnum; /* Processor x Number Register */
277 u32 cpxmaster; /* Processor x Master Number Register */
278 u32 cpxcount; /* Processor x Count Register */
279 u32 cpxcfg0; /* Processor x Configuration 0 Register */
280 u32 cpxcfg1; /* Processor x Configuration 1 Register */
281 u32 cpxcfg2; /* Processor x Configuration 2 Register */
282 u32 cpxcfg3; /* Processor x Configuration 3 Register */
283 u32 cp0type; /* Processor 0 Type Register */
284 u32 cp0num; /* Processor 0 Number Register */
285 u32 cp0master; /* Processor 0 Master Number Register */
286 u32 cp0count; /* Processor 0 Count Register */
287 u32 cp0cfg0; /* Processor 0 Configuration 0 Register */
288 u32 cp0cfg1; /* Processor 0 Configuration 1 Register */
289 u32 cp0cfg2; /* Processor 0 Configuration 2 Register */
290 u32 cp0cfg3; /* Processor 0 Configuration 3 Register */
291 u32 cp1type; /* Processor 1 Type Register */
292 u32 cp1num; /* Processor 1 Number Register */
293 u32 cp1master; /* Processor 1 Master Number Register */
294 u32 cp1count; /* Processor 1 Count Register */
295 u32 cp1cfg0; /* Processor 1 Configuration 0 Register */
296 u32 cp1cfg1; /* Processor 1 Configuration 1 Register */
297 u32 cp1cfg2; /* Processor 1 Configuration 2 Register */
298 u32 cp1cfg3; /* Processor 1 Configuration 3 Register */
299 u32 reserved_0x060[232];
300 u32 ocmdr0; /* On-Chip Memory Descriptor Register */
301 u32 reserved_0x404[2];
302 u32 ocmdr3; /* On-Chip Memory Descriptor Register */
303 u32 reserved_0x410[28];
304 u32 tcmdr[4]; /* Generic Tightly Coupled Memory Descriptor Register */
305 u32 reserved_0x490[28];
306 u32 cpce0; /* Core Parity Checking Enable Register 0 */
307 u32 reserved_0x504[191];
308 u32 ircp0ir; /* Interrupt Router CP0 Interrupt Register */
309 u32 ircp1ir; /* Interrupt Router CP1 Interrupt Register */
310 u32 reserved_0x808[6];
311 u32 ircpgir; /* Interrupt Router CPU Generate Interrupt Register */
312 u32 reserved_0x824[23];
313 u16 irsprc[176]; /* Interrupt Router Shared Peripheral Routing Control Register */
314 u32 reserved_0x9e0[136];
315 u32 iahbbe0; /* Gasket Burst Enable Register */
316 u32 reserved_0xc04[63];
317 u32 ipcge; /* Interconnect Parity Checking Global Enable Register */
318 u32 reserved_0xd04[3];
319 u32 ipce[4]; /* Interconnect Parity Checking Enable Register */
320 u32 reserved_0xd20[8];
321 u32 ipcgie; /* Interconnect Parity Checking Global Injection Enable Register */
322 u32 reserved_0xd44[3];
323 u32 ipcie[4]; /* Interconnect Parity Checking Injection Enable Register */