Lines Matching +full:5 +full:mhz
17 u32 apll_con[5];
19 u32 dpll_con[5];
21 u32 cpll_con[5];
23 u32 gpll_con[5];
32 u32 npll_con[5];
47 #define MHz 1000000 macro
49 #define OSC_HZ (24 * MHz)
50 #define APLL_HZ (600 * MHz)
51 #define GPLL_HZ (576 * MHz)
52 #define CPLL_HZ (594 * MHz)
54 #define CLK_CORE_HZ (600 * MHz)
55 #define ACLKM_CORE_HZ (300 * MHz)
56 #define PCLK_DBG_HZ (300 * MHz)
62 #define PWM_CLOCK_HZ (74 * MHz)