Lines Matching +full:tsi +full:- +full:channel +full:- +full:mask
2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
12 * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
13 * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
22 /* FIXME hack so that SA-1111.h will work [cb] */
96 #define DCSR0 0x40000000 /* DMA Control / Status Register for Channel 0 */
97 #define DCSR1 0x40000004 /* DMA Control / Status Register for Channel 1 */
98 #define DCSR2 0x40000008 /* DMA Control / Status Register for Channel 2 */
99 #define DCSR3 0x4000000c /* DMA Control / Status Register for Channel 3 */
100 #define DCSR4 0x40000010 /* DMA Control / Status Register for Channel 4 */
101 #define DCSR5 0x40000014 /* DMA Control / Status Register for Channel 5 */
102 #define DCSR6 0x40000018 /* DMA Control / Status Register for Channel 6 */
103 #define DCSR7 0x4000001c /* DMA Control / Status Register for Channel 7 */
104 #define DCSR8 0x40000020 /* DMA Control / Status Register for Channel 8 */
105 #define DCSR9 0x40000024 /* DMA Control / Status Register for Channel 9 */
106 #define DCSR10 0x40000028 /* DMA Control / Status Register for Channel 10 */
107 #define DCSR11 0x4000002c /* DMA Control / Status Register for Channel 11 */
108 #define DCSR12 0x40000030 /* DMA Control / Status Register for Channel 12 */
109 #define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */
110 #define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */
111 #define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */
113 #define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */
114 #define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */
115 #define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */
116 #define DCSR19 0x4000004c /* DMA Control / Status Register for Channel 19 */
117 #define DCSR20 0x40000050 /* DMA Control / Status Register for Channel 20 */
118 #define DCSR21 0x40000054 /* DMA Control / Status Register for Channel 21 */
119 #define DCSR22 0x40000058 /* DMA Control / Status Register for Channel 22 */
120 #define DCSR23 0x4000005c /* DMA Control / Status Register for Channel 23 */
121 #define DCSR24 0x40000060 /* DMA Control / Status Register for Channel 24 */
122 #define DCSR25 0x40000064 /* DMA Control / Status Register for Channel 25 */
123 #define DCSR26 0x40000068 /* DMA Control / Status Register for Channel 26 */
124 #define DCSR27 0x4000006c /* DMA Control / Status Register for Channel 27 */
125 #define DCSR28 0x40000070 /* DMA Control / Status Register for Channel 28 */
126 #define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */
127 #define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */
128 #define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */
134 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
147 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
148 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
155 #define DRCMR0 0x40000100 /* Request to Channel Map Register for DREQ 0 */
156 #define DRCMR1 0x40000104 /* Request to Channel Map Register for DREQ 1 */
157 #define DRCMR2 0x40000108 /* Request to Channel Map Register for I2S receive Request */
158 #define DRCMR3 0x4000010c /* Request to Channel Map Register for I2S transmit Request */
159 #define DRCMR4 0x40000110 /* Request to Channel Map Register for BTUART receive Request */
160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */
161 #define DRCMR6 0x40000118 /* Request to Channel Map Register for FFUART receive Request */
162 #define DRCMR7 0x4000011c /* Request to Channel Map Register for FFUART transmit Request */
163 #define DRCMR8 0x40000120 /* Request to Channel Map Register for AC97 microphone Request */
164 #define DRCMR9 0x40000124 /* Request to Channel Map Register for AC97 modem receive Request */
165 #define DRCMR10 0x40000128 /* Request to Channel Map Register for AC97 modem transmit Request */
166 #define DRCMR11 0x4000012c /* Request to Channel Map Register for AC97 audio receive Request */
167 #define DRCMR12 0x40000130 /* Request to Channel Map Register for AC97 audio transmit Request */
168 #define DRCMR13 0x40000134 /* Request to Channel Map Register for SSP receive Request */
169 #define DRCMR14 0x40000138 /* Request to Channel Map Register for SSP transmit Request */
172 #define DRCMR17 0x40000144 /* Request to Channel Map Register for ICP receive Request */
173 #define DRCMR18 0x40000148 /* Request to Channel Map Register for ICP transmit Request */
174 #define DRCMR19 0x4000014c /* Request to Channel Map Register for STUART receive Request */
175 #define DRCMR20 0x40000150 /* Request to Channel Map Register for STUART transmit Request */
176 #define DRCMR21 0x40000154 /* Request to Channel Map Register for MMC receive Request */
177 #define DRCMR22 0x40000158 /* Request to Channel Map Register for MMC transmit Request */
180 #define DRCMR25 0x40000164 /* Request to Channel Map Register for USB endpoint 1 Request */
181 #define DRCMR26 0x40000168 /* Request to Channel Map Register for USB endpoint 2 Request */
182 #define DRCMR27 0x4000016C /* Request to Channel Map Register for USB endpoint 3 Request */
183 #define DRCMR28 0x40000170 /* Request to Channel Map Register for USB endpoint 4 Request */
185 #define DRCMR30 0x40000178 /* Request to Channel Map Register for USB endpoint 6 Request */
186 #define DRCMR31 0x4000017C /* Request to Channel Map Register for USB endpoint 7 Request */
187 #define DRCMR32 0x40000180 /* Request to Channel Map Register for USB endpoint 8 Request */
188 #define DRCMR33 0x40000184 /* Request to Channel Map Register for USB endpoint 9 Request */
190 #define DRCMR35 0x4000018C /* Request to Channel Map Register for USB endpoint 11 Request */
191 #define DRCMR36 0x40000190 /* Request to Channel Map Register for USB endpoint 12 Request */
192 #define DRCMR37 0x40000194 /* Request to Channel Map Register for USB endpoint 13 Request */
193 #define DRCMR38 0x40000198 /* Request to Channel Map Register for USB endpoint 14 Request */
196 #define DRCMR68 0x40001110 /* Request to Channel Map Register for Camera FIFO 0 Request */
197 #define DRCMR69 0x40001114 /* Request to Channel Map Register for Camera FIFO 1 Request */
198 #define DRCMR70 0x40001118 /* Request to Channel Map Register for Camera FIFO 2 Request */
221 #define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */
223 #define DDADR0 0x40000200 /* DMA Descriptor Address Register Channel 0 */
224 #define DSADR0 0x40000204 /* DMA Source Address Register Channel 0 */
225 #define DTADR0 0x40000208 /* DMA Target Address Register Channel 0 */
226 #define DCMD0 0x4000020c /* DMA Command Address Register Channel 0 */
227 #define DDADR1 0x40000210 /* DMA Descriptor Address Register Channel 1 */
228 #define DSADR1 0x40000214 /* DMA Source Address Register Channel 1 */
229 #define DTADR1 0x40000218 /* DMA Target Address Register Channel 1 */
230 #define DCMD1 0x4000021c /* DMA Command Address Register Channel 1 */
231 #define DDADR2 0x40000220 /* DMA Descriptor Address Register Channel 2 */
232 #define DSADR2 0x40000224 /* DMA Source Address Register Channel 2 */
233 #define DTADR2 0x40000228 /* DMA Target Address Register Channel 2 */
234 #define DCMD2 0x4000022c /* DMA Command Address Register Channel 2 */
235 #define DDADR3 0x40000230 /* DMA Descriptor Address Register Channel 3 */
236 #define DSADR3 0x40000234 /* DMA Source Address Register Channel 3 */
237 #define DTADR3 0x40000238 /* DMA Target Address Register Channel 3 */
238 #define DCMD3 0x4000023c /* DMA Command Address Register Channel 3 */
239 #define DDADR4 0x40000240 /* DMA Descriptor Address Register Channel 4 */
240 #define DSADR4 0x40000244 /* DMA Source Address Register Channel 4 */
241 #define DTADR4 0x40000248 /* DMA Target Address Register Channel 4 */
242 #define DCMD4 0x4000024c /* DMA Command Address Register Channel 4 */
243 #define DDADR5 0x40000250 /* DMA Descriptor Address Register Channel 5 */
244 #define DSADR5 0x40000254 /* DMA Source Address Register Channel 5 */
245 #define DTADR5 0x40000258 /* DMA Target Address Register Channel 5 */
246 #define DCMD5 0x4000025c /* DMA Command Address Register Channel 5 */
247 #define DDADR6 0x40000260 /* DMA Descriptor Address Register Channel 6 */
248 #define DSADR6 0x40000264 /* DMA Source Address Register Channel 6 */
249 #define DTADR6 0x40000268 /* DMA Target Address Register Channel 6 */
250 #define DCMD6 0x4000026c /* DMA Command Address Register Channel 6 */
251 #define DDADR7 0x40000270 /* DMA Descriptor Address Register Channel 7 */
252 #define DSADR7 0x40000274 /* DMA Source Address Register Channel 7 */
253 #define DTADR7 0x40000278 /* DMA Target Address Register Channel 7 */
254 #define DCMD7 0x4000027c /* DMA Command Address Register Channel 7 */
255 #define DDADR8 0x40000280 /* DMA Descriptor Address Register Channel 8 */
256 #define DSADR8 0x40000284 /* DMA Source Address Register Channel 8 */
257 #define DTADR8 0x40000288 /* DMA Target Address Register Channel 8 */
258 #define DCMD8 0x4000028c /* DMA Command Address Register Channel 8 */
259 #define DDADR9 0x40000290 /* DMA Descriptor Address Register Channel 9 */
260 #define DSADR9 0x40000294 /* DMA Source Address Register Channel 9 */
261 #define DTADR9 0x40000298 /* DMA Target Address Register Channel 9 */
262 #define DCMD9 0x4000029c /* DMA Command Address Register Channel 9 */
263 #define DDADR10 0x400002a0 /* DMA Descriptor Address Register Channel 10 */
264 #define DSADR10 0x400002a4 /* DMA Source Address Register Channel 10 */
265 #define DTADR10 0x400002a8 /* DMA Target Address Register Channel 10 */
266 #define DCMD10 0x400002ac /* DMA Command Address Register Channel 10 */
267 #define DDADR11 0x400002b0 /* DMA Descriptor Address Register Channel 11 */
268 #define DSADR11 0x400002b4 /* DMA Source Address Register Channel 11 */
269 #define DTADR11 0x400002b8 /* DMA Target Address Register Channel 11 */
270 #define DCMD11 0x400002bc /* DMA Command Address Register Channel 11 */
271 #define DDADR12 0x400002c0 /* DMA Descriptor Address Register Channel 12 */
272 #define DSADR12 0x400002c4 /* DMA Source Address Register Channel 12 */
273 #define DTADR12 0x400002c8 /* DMA Target Address Register Channel 12 */
274 #define DCMD12 0x400002cc /* DMA Command Address Register Channel 12 */
275 #define DDADR13 0x400002d0 /* DMA Descriptor Address Register Channel 13 */
276 #define DSADR13 0x400002d4 /* DMA Source Address Register Channel 13 */
277 #define DTADR13 0x400002d8 /* DMA Target Address Register Channel 13 */
278 #define DCMD13 0x400002dc /* DMA Command Address Register Channel 13 */
279 #define DDADR14 0x400002e0 /* DMA Descriptor Address Register Channel 14 */
280 #define DSADR14 0x400002e4 /* DMA Source Address Register Channel 14 */
281 #define DTADR14 0x400002e8 /* DMA Target Address Register Channel 14 */
282 #define DCMD14 0x400002ec /* DMA Command Address Register Channel 14 */
283 #define DDADR15 0x400002f0 /* DMA Descriptor Address Register Channel 15 */
284 #define DSADR15 0x400002f4 /* DMA Source Address Register Channel 15 */
285 #define DTADR15 0x400002f8 /* DMA Target Address Register Channel 15 */
286 #define DCMD15 0x400002fc /* DMA Command Address Register Channel 15 */
293 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
302 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
309 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
354 #define SACR1 0x40400004 /* Serial Audio I 2 S/MSB-Justified Control Register */
355 #define SASR0 0x4040000C /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register …
356 #define SAIMR 0x40400014 /* Serial Audio Interrupt Mask Register */
380 #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
416 #define MCDR 0x40500060 /* Mic-in FIFO Data Register */
451 #define UDCCR_SM (1 << 28) /* Suspend interrupt mask */
453 #define UDCCR_REM (1 << 27) /* Reset interrupt mask */
454 #define UDCCR_RM (1 << 29) /* resume interrupt mask */
456 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
457 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocol Port Support */
458 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol Support */
459 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol Enable */
460 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
478 /* Bulk IN - Endpoint 1,6,11 */
491 /* Bulk OUT - Endpoint 2,7,12 */
504 /* Isochronous IN - Endpoint 3,8,13 */
515 /* Isochronous OUT - Endpoint 4,9,14 */
527 /* Interrupt IN - Endpoint 5,10,15 */
567 #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
568 #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
569 #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
570 #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
571 #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
572 #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
573 #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
574 #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
578 #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
579 #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
580 #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
581 #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
582 #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
583 #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
584 #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
585 #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
616 #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
617 #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
618 #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
619 #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
620 #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
625 #define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */
626 #define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */
627 #define UDCISR1_IRRU (1 << 29) /* IntEn - Resume */
628 #define UDCISR1_IRSU (1 << 28) /* IntEn - Suspend */
629 #define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */
633 #define UDCOTGICR 0x40600018 /* UDC On-The-Go interrupt control */
643 #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising Edge Interrupt Enable */
644 #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling Edge Interrupt Enable */
649 #define UDCCSR0 0x40600100 /* UDC Control/Status register - Endpoint 0 */
660 #define UDCCSRA 0x40600104 /* UDC Control/Status register - Endpoint A */
661 #define UDCCSRB 0x40600108 /* UDC Control/Status register - Endpoint B */
662 #define UDCCSRC 0x4060010C /* UDC Control/Status register - Endpoint C */
663 #define UDCCSRD 0x40600110 /* UDC Control/Status register - Endpoint D */
664 #define UDCCSRE 0x40600114 /* UDC Control/Status register - Endpoint E */
665 #define UDCCSRF 0x40600118 /* UDC Control/Status register - Endpoint F */
666 #define UDCCSRG 0x4060011C /* UDC Control/Status register - Endpoint G */
667 #define UDCCSRH 0x40600120 /* UDC Control/Status register - Endpoint H */
668 #define UDCCSRI 0x40600124 /* UDC Control/Status register - Endpoint I */
669 #define UDCCSRJ 0x40600128 /* UDC Control/Status register - Endpoint J */
670 #define UDCCSRK 0x4060012C /* UDC Control/Status register - Endpoint K */
671 #define UDCCSRL 0x40600130 /* UDC Control/Status register - Endpoint L */
672 #define UDCCSRM 0x40600134 /* UDC Control/Status register - Endpoint M */
673 #define UDCCSRN 0x40600138 /* UDC Control/Status register - Endpoint N */
674 #define UDCCSRP 0x4060013C /* UDC Control/Status register - Endpoint P */
675 #define UDCCSRQ 0x40600140 /* UDC Control/Status register - Endpoint Q */
676 #define UDCCSRR 0x40600144 /* UDC Control/Status register - Endpoint R */
677 #define UDCCSRS 0x40600148 /* UDC Control/Status register - Endpoint S */
678 #define UDCCSRT 0x4060014C /* UDC Control/Status register - Endpoint T */
679 #define UDCCSRU 0x40600150 /* UDC Control/Status register - Endpoint U */
680 #define UDCCSRV 0x40600154 /* UDC Control/Status register - Endpoint V */
681 #define UDCCSRW 0x40600158 /* UDC Control/Status register - Endpoint W */
682 #define UDCCSRX 0x4060015C /* UDC Control/Status register - Endpoint X */
697 #define UDCBCR0 0x40600200 /* Byte Count Register - EP0 */
698 #define UDCBCRA 0x40600204 /* Byte Count Register - EPA */
699 #define UDCBCRB 0x40600208 /* Byte Count Register - EPB */
700 #define UDCBCRC 0x4060020C /* Byte Count Register - EPC */
701 #define UDCBCRD 0x40600210 /* Byte Count Register - EPD */
702 #define UDCBCRE 0x40600214 /* Byte Count Register - EPE */
703 #define UDCBCRF 0x40600218 /* Byte Count Register - EPF */
704 #define UDCBCRG 0x4060021C /* Byte Count Register - EPG */
705 #define UDCBCRH 0x40600220 /* Byte Count Register - EPH */
706 #define UDCBCRI 0x40600224 /* Byte Count Register - EPI */
707 #define UDCBCRJ 0x40600228 /* Byte Count Register - EPJ */
708 #define UDCBCRK 0x4060022C /* Byte Count Register - EPK */
709 #define UDCBCRL 0x40600230 /* Byte Count Register - EPL */
710 #define UDCBCRM 0x40600234 /* Byte Count Register - EPM */
711 #define UDCBCRN 0x40600238 /* Byte Count Register - EPN */
712 #define UDCBCRP 0x4060023C /* Byte Count Register - EPP */
713 #define UDCBCRQ 0x40600240 /* Byte Count Register - EPQ */
714 #define UDCBCRR 0x40600244 /* Byte Count Register - EPR */
715 #define UDCBCRS 0x40600248 /* Byte Count Register - EPS */
716 #define UDCBCRT 0x4060024C /* Byte Count Register - EPT */
717 #define UDCBCRU 0x40600250 /* Byte Count Register - EPU */
718 #define UDCBCRV 0x40600254 /* Byte Count Register - EPV */
719 #define UDCBCRW 0x40600258 /* Byte Count Register - EPW */
720 #define UDCBCRX 0x4060025C /* Byte Count Register - EPX */
723 #define UDCDR0 0x40600300 /* Data Register - EP0 */
724 #define UDCDRA 0x40600304 /* Data Register - EPA */
725 #define UDCDRB 0x40600308 /* Data Register - EPB */
726 #define UDCDRC 0x4060030C /* Data Register - EPC */
727 #define UDCDRD 0x40600310 /* Data Register - EPD */
728 #define UDCDRE 0x40600314 /* Data Register - EPE */
729 #define UDCDRF 0x40600318 /* Data Register - EPF */
730 #define UDCDRG 0x4060031C /* Data Register - EPG */
731 #define UDCDRH 0x40600320 /* Data Register - EPH */
732 #define UDCDRI 0x40600324 /* Data Register - EPI */
733 #define UDCDRJ 0x40600328 /* Data Register - EPJ */
734 #define UDCDRK 0x4060032C /* Data Register - EPK */
735 #define UDCDRL 0x40600330 /* Data Register - EPL */
736 #define UDCDRM 0x40600334 /* Data Register - EPM */
737 #define UDCDRN 0x40600338 /* Data Register - EPN */
738 #define UDCDRP 0x4060033C /* Data Register - EPP */
739 #define UDCDRQ 0x40600340 /* Data Register - EPQ */
740 #define UDCDRR 0x40600344 /* Data Register - EPR */
741 #define UDCDRS 0x40600348 /* Data Register - EPS */
742 #define UDCDRT 0x4060034C /* Data Register - EPT */
743 #define UDCDRU 0x40600350 /* Data Register - EPU */
744 #define UDCDRV 0x40600354 /* Data Register - EPV */
745 #define UDCDRW 0x40600358 /* Data Register - EPW */
746 #define UDCDRX 0x4060035C /* Data Register - EPX */
912 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
958 #define OSSR_M4 (1 << 4) /* Match status channel 4 */
959 #define OSSR_M3 (1 << 3) /* Match status channel 3 */
960 #define OSSR_M2 (1 << 2) /* Match status channel 2 */
961 #define OSSR_M1 (1 << 1) /* Match status channel 1 */
962 #define OSSR_M0 (1 << 0) /* Match status channel 0 */
966 #define OIER_E4 (1 << 4) /* Interrupt enable channel 4 */
967 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
968 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
969 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
970 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
1006 #define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */
1089 #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
1090 #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
1139 #define ICMR 0x40D00004 /* Interrupt Controller Mask Register */
1148 #define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */
1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */
1159 #define GPLR1 0x40E00004 /* GPIO Pin-Level Register GPIO<63:32> */
1160 #define GPLR2 0x40E00008 /* GPIO Pin-Level Register GPIO<80:64> */
1174 #define GRER0 0x40E00030 /* GPIO Rising-Edge Detect Register GPIO<31:0> */
1175 #define GRER1 0x40E00034 /* GPIO Rising-Edge Detect Register GPIO<63:32> */
1176 #define GRER2 0x40E00038 /* GPIO Rising-Edge Detect Register GPIO<80:64> */
1178 #define GFER0 0x40E0003C /* GPIO Falling-Edge Detect Register GPIO<31:0> */
1179 #define GFER1 0x40E00040 /* GPIO Falling-Edge Detect Register GPIO<63:32> */
1180 #define GFER2 0x40E00044 /* GPIO Falling-Edge Detect Register GPIO<80:64> */
1194 #define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */
1198 #define GRER3 0x40E00130 /* GPIO Rising-Edge Detect Register GPIO<127:96> */
1199 #define GFER3 0x40E0013C /* GPIO Falling-Edge Detect Register GPIO<127:96> */
1206 #define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */
1207 #define GSDR1 0x40E00404 /* Bit-wise Set of GPDR[63:32] */
1208 #define GSDR2 0x40E00408 /* Bit-wise Set of GPDR[95:64] */
1209 #define GSDR3 0x40E0040C /* Bit-wise Set of GPDR[127:96] */
1211 #define GCDR0 0x40E00420 /* Bit-wise Clear of GPDR[31:0] */
1212 #define GCDR1 0x40E00424 /* Bit-wise Clear of GPDR[63:32] */
1213 #define GCDR2 0x40E00428 /* Bit-wise Clear of GPDR[95:64] */
1214 #define GCDR3 0x40E0042C /* Bit-wise Clear of GPDR[127:96] */
1274 * Multi-function Pin Registers:
1662 /* MFPR Bit Definitions, see 4-10, Vol. 1 */
1919 #define PWER 0x40F50010 /* Power Manager Wake-up Enable Register */
1920 #define PWSR 0x40F50014 /* Power Manager Wake-up Status Register */
1922 #define DCDCSR 0x40F50080 /* DC-DC Controller Status Register */
1974 #define PWER 0x40F0000C /* Power Manager Wake-up Enable Register */
1975 #define PRER 0x40F00010 /* Power Manager GPIO Rising-Edge Detect Enable Register */
1976 #define PFER 0x40F00014 /* Power Manager GPIO Falling-Edge Detect Enable Register */
1979 #define PGSR0 0x40F00020 /* Power Manager GPIO Sleep State Register for GP[31-0] */
1980 #define PGSR1 0x40F00024 /* Power Manager GPIO Sleep State Register for GP[63-32] */
1981 #define PGSR2 0x40F00028 /* Power Manager GPIO Sleep State Register for GP[84-64] */
1982 #define PGSR3 0x40F0002C /* Power Manager GPIO Sleep State Register for GP[118-96] */
1989 #define PKWR 0x40F00050 /* Power Manager KB Wake-up Enable Reg */
1990 #define PKSR 0x40F00054 /* Power Manager KB Level-Detect Register */
2047 #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
2078 #define MMC_I_MASK 0x41100028 /* Interrupt Mask */
2095 #define DFBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */
2096 #define DFBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */
2103 #define FDADR0 0x44000200 /* DMA Channel 0 Frame Descriptor Address Register */
2104 #define FSADR0 0x44000204 /* DMA Channel 0 Frame Source Address Register */
2105 #define FIDR0 0x44000208 /* DMA Channel 0 Frame ID Register */
2106 #define LDCMD0 0x4400020C /* DMA Channel 0 Command Register */
2107 #define FDADR1 0x44000210 /* DMA Channel 1 Frame Descriptor Address Register */
2108 #define FSADR1 0x44000214 /* DMA Channel 1 Frame Source Address Register */
2109 #define FIDR1 0x44000218 /* DMA Channel 1 Frame ID Register */
2110 #define LDCMD1 0x4400021C /* DMA Channel 1 Command Register */
2115 #define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
2116 #define LCCR0_SFM (1 << 4) /* Start of frame mask */
2117 #define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
2118 #define LCCR0_EFM (1 << 6) /* End of Frame mask */
2123 #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
2126 #define LCCR0_BM (1 << 20) /* Branch mask */
2127 #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
2130 #define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */
2131 #define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */
2134 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
2136 (((Pixel) - 1) << FShft (LCCR1_PPL))
2141 (((Tpix) - 1) << FShft (LCCR1_HSW))
2143 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
2144 /* count - 1 [Tpix] */
2145 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
2147 (((Tpix) - 1) << FShft (LCCR1_ELW))
2149 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
2150 /* Wait count - 1 [Tpix] */
2151 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
2153 (((Tpix) - 1) << FShft (LCCR1_BLW))
2156 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
2158 (((Line) - 1) << FShft (LCCR2_LPP))
2161 /* Width - 1 [Tln] (L_FCLK) */
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2166 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
2172 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
2288 #define FLYCNFG 0x48100020 /* Fly-by DMA DVAL[1:0] polarities */
2403 #define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
2455 #define SXLCR 0x48000018 /* LCR value to be written to SDRAM-Timing Synchronous Flash */
2466 #define BOOT_DEF 0x48000044 /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
2471 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
2472 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
2473 #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
2474 #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
2475 #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
2504 #define FBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */
2505 #define FBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */
2506 #define FBR2 0x44000028 /* DMA Channel 2 Frame Branch Register */
2507 #define FBR3 0x4400002C /* DMA Channel 3 Frame Branch Register */
2508 #define FBR4 0x44000030 /* DMA Channel 4 Frame Branch Register */
2509 #define FDADR2 0x44000220 /* DMA Channel 2 Frame Descriptor Address Register */
2510 #define FSADR2 0x44000224 /* DMA Channel 2 Frame Source Address Register */
2511 #define FIDR2 0x44000228 /* DMA Channel 2 Frame ID Register */
2512 #define LDCMD2 0x4400022C /* DMA Channel 2 Command Register */
2513 #define FDADR3 0x44000230 /* DMA Channel 3 Frame Descriptor Address Register */
2514 #define FSADR3 0x44000234 /* DMA Channel 3 Frame Source Address Register */
2515 #define FIDR3 0x44000238 /* DMA Channel 3 Frame ID Register */
2516 #define LDCMD3 0x4400023C /* DMA Channel 3 Command Register */
2517 #define FDADR4 0x44000240 /* DMA Channel 4 Frame Descriptor Address Register */
2518 #define FSADR4 0x44000244 /* DMA Channel 4 Frame Source Address Register */
2519 #define FIDR4 0x44000248 /* DMA Channel 4 Frame ID Register */
2520 #define LDCMD4 0x4400024C /* DMA Channel 4 Command Register */
2521 #define FDADR5 0x44000250 /* DMA Channel 5 Frame Descriptor Address Register */
2522 #define FSADR5 0x44000254 /* DMA Channel 5 Frame Source Address Register */
2523 #define FIDR5 0x44000258 /* DMA Channel 5 Frame ID Register */
2524 #define LDCMD5 0x4400025C /* DMA Channel 5 Command Register */
2532 #define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */
2533 #define FBR6 0x44000114 /* DMA Channel 6 Frame Branch Register */
2538 #define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */
2539 #define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */
2540 #define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */
2541 #define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */
2542 #define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */
2543 #define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */
2545 #define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */
2546 #define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */
2547 #define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */
2548 #define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */
2549 #define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */
2550 #define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */
2552 #define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */
2553 #define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */
2554 #define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */
2555 #define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */
2556 #define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */
2557 #define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */
2559 #define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */
2560 #define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */
2561 #define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */
2562 #define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */
2563 #define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */
2564 #define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */
2627 #define PKWR 0x40F00050 /* Power Manager KB Wake-Up Enable Reg */
2628 #define PKSR 0x40F00054 /* Power Manager KB Level-Detect Status Reg */