Lines Matching +full:rotary +full:- +full:encoder
2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
12 * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
13 * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
22 /* FIXME hack so that SA-1111.h will work [cb] */
134 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
147 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
148 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
302 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
309 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
354 #define SACR1 0x40400004 /* Serial Audio I 2 S/MSB-Justified Control Register */
355 #define SASR0 0x4040000C /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register …
380 #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
416 #define MCDR 0x40500060 /* Mic-in FIFO Data Register */
456 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
457 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocol Port Support */
458 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol Support */
459 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol Enable */
460 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
478 /* Bulk IN - Endpoint 1,6,11 */
491 /* Bulk OUT - Endpoint 2,7,12 */
504 /* Isochronous IN - Endpoint 3,8,13 */
515 /* Isochronous OUT - Endpoint 4,9,14 */
527 /* Interrupt IN - Endpoint 5,10,15 */
616 #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
617 #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
618 #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
619 #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
620 #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
625 #define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */
626 #define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */
627 #define UDCISR1_IRRU (1 << 29) /* IntEn - Resume */
628 #define UDCISR1_IRSU (1 << 28) /* IntEn - Suspend */
629 #define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */
633 #define UDCOTGICR 0x40600018 /* UDC On-The-Go interrupt control */
643 #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising Edge Interrupt Enable */
644 #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling Edge Interrupt Enable */
649 #define UDCCSR0 0x40600100 /* UDC Control/Status register - Endpoint 0 */
660 #define UDCCSRA 0x40600104 /* UDC Control/Status register - Endpoint A */
661 #define UDCCSRB 0x40600108 /* UDC Control/Status register - Endpoint B */
662 #define UDCCSRC 0x4060010C /* UDC Control/Status register - Endpoint C */
663 #define UDCCSRD 0x40600110 /* UDC Control/Status register - Endpoint D */
664 #define UDCCSRE 0x40600114 /* UDC Control/Status register - Endpoint E */
665 #define UDCCSRF 0x40600118 /* UDC Control/Status register - Endpoint F */
666 #define UDCCSRG 0x4060011C /* UDC Control/Status register - Endpoint G */
667 #define UDCCSRH 0x40600120 /* UDC Control/Status register - Endpoint H */
668 #define UDCCSRI 0x40600124 /* UDC Control/Status register - Endpoint I */
669 #define UDCCSRJ 0x40600128 /* UDC Control/Status register - Endpoint J */
670 #define UDCCSRK 0x4060012C /* UDC Control/Status register - Endpoint K */
671 #define UDCCSRL 0x40600130 /* UDC Control/Status register - Endpoint L */
672 #define UDCCSRM 0x40600134 /* UDC Control/Status register - Endpoint M */
673 #define UDCCSRN 0x40600138 /* UDC Control/Status register - Endpoint N */
674 #define UDCCSRP 0x4060013C /* UDC Control/Status register - Endpoint P */
675 #define UDCCSRQ 0x40600140 /* UDC Control/Status register - Endpoint Q */
676 #define UDCCSRR 0x40600144 /* UDC Control/Status register - Endpoint R */
677 #define UDCCSRS 0x40600148 /* UDC Control/Status register - Endpoint S */
678 #define UDCCSRT 0x4060014C /* UDC Control/Status register - Endpoint T */
679 #define UDCCSRU 0x40600150 /* UDC Control/Status register - Endpoint U */
680 #define UDCCSRV 0x40600154 /* UDC Control/Status register - Endpoint V */
681 #define UDCCSRW 0x40600158 /* UDC Control/Status register - Endpoint W */
682 #define UDCCSRX 0x4060015C /* UDC Control/Status register - Endpoint X */
697 #define UDCBCR0 0x40600200 /* Byte Count Register - EP0 */
698 #define UDCBCRA 0x40600204 /* Byte Count Register - EPA */
699 #define UDCBCRB 0x40600208 /* Byte Count Register - EPB */
700 #define UDCBCRC 0x4060020C /* Byte Count Register - EPC */
701 #define UDCBCRD 0x40600210 /* Byte Count Register - EPD */
702 #define UDCBCRE 0x40600214 /* Byte Count Register - EPE */
703 #define UDCBCRF 0x40600218 /* Byte Count Register - EPF */
704 #define UDCBCRG 0x4060021C /* Byte Count Register - EPG */
705 #define UDCBCRH 0x40600220 /* Byte Count Register - EPH */
706 #define UDCBCRI 0x40600224 /* Byte Count Register - EPI */
707 #define UDCBCRJ 0x40600228 /* Byte Count Register - EPJ */
708 #define UDCBCRK 0x4060022C /* Byte Count Register - EPK */
709 #define UDCBCRL 0x40600230 /* Byte Count Register - EPL */
710 #define UDCBCRM 0x40600234 /* Byte Count Register - EPM */
711 #define UDCBCRN 0x40600238 /* Byte Count Register - EPN */
712 #define UDCBCRP 0x4060023C /* Byte Count Register - EPP */
713 #define UDCBCRQ 0x40600240 /* Byte Count Register - EPQ */
714 #define UDCBCRR 0x40600244 /* Byte Count Register - EPR */
715 #define UDCBCRS 0x40600248 /* Byte Count Register - EPS */
716 #define UDCBCRT 0x4060024C /* Byte Count Register - EPT */
717 #define UDCBCRU 0x40600250 /* Byte Count Register - EPU */
718 #define UDCBCRV 0x40600254 /* Byte Count Register - EPV */
719 #define UDCBCRW 0x40600258 /* Byte Count Register - EPW */
720 #define UDCBCRX 0x4060025C /* Byte Count Register - EPX */
723 #define UDCDR0 0x40600300 /* Data Register - EP0 */
724 #define UDCDRA 0x40600304 /* Data Register - EPA */
725 #define UDCDRB 0x40600308 /* Data Register - EPB */
726 #define UDCDRC 0x4060030C /* Data Register - EPC */
727 #define UDCDRD 0x40600310 /* Data Register - EPD */
728 #define UDCDRE 0x40600314 /* Data Register - EPE */
729 #define UDCDRF 0x40600318 /* Data Register - EPF */
730 #define UDCDRG 0x4060031C /* Data Register - EPG */
731 #define UDCDRH 0x40600320 /* Data Register - EPH */
732 #define UDCDRI 0x40600324 /* Data Register - EPI */
733 #define UDCDRJ 0x40600328 /* Data Register - EPJ */
734 #define UDCDRK 0x4060032C /* Data Register - EPK */
735 #define UDCDRL 0x40600330 /* Data Register - EPL */
736 #define UDCDRM 0x40600334 /* Data Register - EPM */
737 #define UDCDRN 0x40600338 /* Data Register - EPN */
738 #define UDCDRP 0x4060033C /* Data Register - EPP */
739 #define UDCDRQ 0x40600340 /* Data Register - EPQ */
740 #define UDCDRR 0x40600344 /* Data Register - EPR */
741 #define UDCDRS 0x40600348 /* Data Register - EPS */
742 #define UDCDRT 0x4060034C /* Data Register - EPT */
743 #define UDCDRU 0x40600350 /* Data Register - EPU */
744 #define UDCDRV 0x40600354 /* Data Register - EPV */
745 #define UDCDRW 0x40600358 /* Data Register - EPW */
746 #define UDCDRX 0x4060035C /* Data Register - EPX */
912 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
1089 #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
1090 #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
1158 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */
1159 #define GPLR1 0x40E00004 /* GPIO Pin-Level Register GPIO<63:32> */
1160 #define GPLR2 0x40E00008 /* GPIO Pin-Level Register GPIO<80:64> */
1174 #define GRER0 0x40E00030 /* GPIO Rising-Edge Detect Register GPIO<31:0> */
1175 #define GRER1 0x40E00034 /* GPIO Rising-Edge Detect Register GPIO<63:32> */
1176 #define GRER2 0x40E00038 /* GPIO Rising-Edge Detect Register GPIO<80:64> */
1178 #define GFER0 0x40E0003C /* GPIO Falling-Edge Detect Register GPIO<31:0> */
1179 #define GFER1 0x40E00040 /* GPIO Falling-Edge Detect Register GPIO<63:32> */
1180 #define GFER2 0x40E00044 /* GPIO Falling-Edge Detect Register GPIO<80:64> */
1194 #define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */
1198 #define GRER3 0x40E00130 /* GPIO Rising-Edge Detect Register GPIO<127:96> */
1199 #define GFER3 0x40E0013C /* GPIO Falling-Edge Detect Register GPIO<127:96> */
1206 #define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */
1207 #define GSDR1 0x40E00404 /* Bit-wise Set of GPDR[63:32] */
1208 #define GSDR2 0x40E00408 /* Bit-wise Set of GPDR[95:64] */
1209 #define GSDR3 0x40E0040C /* Bit-wise Set of GPDR[127:96] */
1211 #define GCDR0 0x40E00420 /* Bit-wise Clear of GPDR[31:0] */
1212 #define GCDR1 0x40E00424 /* Bit-wise Clear of GPDR[63:32] */
1213 #define GCDR2 0x40E00428 /* Bit-wise Clear of GPDR[95:64] */
1214 #define GCDR3 0x40E0042C /* Bit-wise Clear of GPDR[127:96] */
1274 * Multi-function Pin Registers:
1662 /* MFPR Bit Definitions, see 4-10, Vol. 1 */
1919 #define PWER 0x40F50010 /* Power Manager Wake-up Enable Register */
1920 #define PWSR 0x40F50014 /* Power Manager Wake-up Status Register */
1922 #define DCDCSR 0x40F50080 /* DC-DC Controller Status Register */
1974 #define PWER 0x40F0000C /* Power Manager Wake-up Enable Register */
1975 #define PRER 0x40F00010 /* Power Manager GPIO Rising-Edge Detect Enable Register */
1976 #define PFER 0x40F00014 /* Power Manager GPIO Falling-Edge Detect Enable Register */
1979 #define PGSR0 0x40F00020 /* Power Manager GPIO Sleep State Register for GP[31-0] */
1980 #define PGSR1 0x40F00024 /* Power Manager GPIO Sleep State Register for GP[63-32] */
1981 #define PGSR2 0x40F00028 /* Power Manager GPIO Sleep State Register for GP[84-64] */
1982 #define PGSR3 0x40F0002C /* Power Manager GPIO Sleep State Register for GP[118-96] */
1989 #define PKWR 0x40F00050 /* Power Manager KB Wake-up Enable Reg */
1990 #define PKSR 0x40F00054 /* Power Manager KB Level-Detect Register */
2047 #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
2134 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
2136 (((Pixel) - 1) << FShft (LCCR1_PPL))
2141 (((Tpix) - 1) << FShft (LCCR1_HSW))
2143 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
2144 /* count - 1 [Tpix] */
2145 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
2147 (((Tpix) - 1) << FShft (LCCR1_ELW))
2149 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
2150 /* Wait count - 1 [Tpix] */
2151 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
2153 (((Tpix) - 1) << FShft (LCCR1_BLW))
2156 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
2158 (((Line) - 1) << FShft (LCCR2_LPP))
2161 /* Width - 1 [Tln] (L_FCLK) */
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2166 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
2172 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
2288 #define FLYCNFG 0x48100020 /* Fly-by DMA DVAL[1:0] polarities */
2403 #define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
2455 #define SXLCR 0x48000018 /* LCR value to be written to SDRAM-Timing Synchronous Flash */
2466 #define BOOT_DEF 0x48000044 /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
2471 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
2472 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
2473 #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
2474 #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
2475 #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
2574 #define KPREC 0x41500010 /* Keypad Intefcace Rotary Encoder register */
2599 #define KPC_DEE0 (0x1 << 2) /* Rotary Encoder 0 Enable */
2627 #define PKWR 0x40F00050 /* Power Manager KB Wake-Up Enable Reg */
2628 #define PKSR 0x40F00054 /* Power Manager KB Level-Detect Status Reg */