Lines Matching +full:0 +full:x0202
23 * M0 - Mode 0
28 #define IDIS (0 << 8)
30 #define PTD (0 << 4)
32 #define DIS (0 << 3)
41 #define M0 0
56 #define CONTROL_PADCONF_SDRC_D0 0x0030
57 #define CONTROL_PADCONF_SDRC_D1 0x0032
58 #define CONTROL_PADCONF_SDRC_D2 0x0034
59 #define CONTROL_PADCONF_SDRC_D3 0x0036
60 #define CONTROL_PADCONF_SDRC_D4 0x0038
61 #define CONTROL_PADCONF_SDRC_D5 0x003A
62 #define CONTROL_PADCONF_SDRC_D6 0x003C
63 #define CONTROL_PADCONF_SDRC_D7 0x003E
64 #define CONTROL_PADCONF_SDRC_D8 0x0040
65 #define CONTROL_PADCONF_SDRC_D9 0x0042
66 #define CONTROL_PADCONF_SDRC_D10 0x0044
67 #define CONTROL_PADCONF_SDRC_D11 0x0046
68 #define CONTROL_PADCONF_SDRC_D12 0x0048
69 #define CONTROL_PADCONF_SDRC_D13 0x004A
70 #define CONTROL_PADCONF_SDRC_D14 0x004C
71 #define CONTROL_PADCONF_SDRC_D15 0x004E
72 #define CONTROL_PADCONF_SDRC_D16 0x0050
73 #define CONTROL_PADCONF_SDRC_D17 0x0052
74 #define CONTROL_PADCONF_SDRC_D18 0x0054
75 #define CONTROL_PADCONF_SDRC_D19 0x0056
76 #define CONTROL_PADCONF_SDRC_D20 0x0058
77 #define CONTROL_PADCONF_SDRC_D21 0x005A
78 #define CONTROL_PADCONF_SDRC_D22 0x005C
79 #define CONTROL_PADCONF_SDRC_D23 0x005E
80 #define CONTROL_PADCONF_SDRC_D24 0x0060
81 #define CONTROL_PADCONF_SDRC_D25 0x0062
82 #define CONTROL_PADCONF_SDRC_D26 0x0064
83 #define CONTROL_PADCONF_SDRC_D27 0x0066
84 #define CONTROL_PADCONF_SDRC_D28 0x0068
85 #define CONTROL_PADCONF_SDRC_D29 0x006A
86 #define CONTROL_PADCONF_SDRC_D30 0x006C
87 #define CONTROL_PADCONF_SDRC_D31 0x006E
88 #define CONTROL_PADCONF_SDRC_CLK 0x0070
89 #define CONTROL_PADCONF_SDRC_DQS0 0x0072
90 #define CONTROL_PADCONF_SDRC_DQS1 0x0074
91 #define CONTROL_PADCONF_SDRC_DQS2 0x0076
92 #define CONTROL_PADCONF_SDRC_DQS3 0x0078
93 #define CONTROL_PADCONF_SDRC_BA0 0x05A0
94 #define CONTROL_PADCONF_SDRC_BA1 0x05A2
95 #define CONTROL_PADCONF_SDRC_A0 0x05A4
96 #define CONTROL_PADCONF_SDRC_A1 0x05A6
97 #define CONTROL_PADCONF_SDRC_A2 0x05A8
98 #define CONTROL_PADCONF_SDRC_A3 0x05AA
99 #define CONTROL_PADCONF_SDRC_A4 0x05AC
100 #define CONTROL_PADCONF_SDRC_A5 0x05AE
101 #define CONTROL_PADCONF_SDRC_A6 0x05B0
102 #define CONTROL_PADCONF_SDRC_A7 0x05B2
103 #define CONTROL_PADCONF_SDRC_A8 0x05B4
104 #define CONTROL_PADCONF_SDRC_A9 0x05B6
105 #define CONTROL_PADCONF_SDRC_A10 0x05B8
106 #define CONTROL_PADCONF_SDRC_A11 0x05BA
107 #define CONTROL_PADCONF_SDRC_A12 0x05BC
108 #define CONTROL_PADCONF_SDRC_A13 0x05BE
109 #define CONTROL_PADCONF_SDRC_A14 0x05C0
110 #define CONTROL_PADCONF_SDRC_NCS0 0x05C2
111 #define CONTROL_PADCONF_SDRC_NCS1 0x05C4
112 #define CONTROL_PADCONF_SDRC_NCLK 0x05C6
113 #define CONTROL_PADCONF_SDRC_NRAS 0x05C8
114 #define CONTROL_PADCONF_SDRC_NCAS 0x05CA
115 #define CONTROL_PADCONF_SDRC_NWE 0x05CC
116 #define CONTROL_PADCONF_SDRC_DM0 0x05CE
117 #define CONTROL_PADCONF_SDRC_DM1 0x05D0
118 #define CONTROL_PADCONF_SDRC_DM2 0x05D2
119 #define CONTROL_PADCONF_SDRC_DM3 0x05D4
121 #define CONTROL_PADCONF_GPMC_A1 0x007A
122 #define CONTROL_PADCONF_GPMC_A2 0x007C
123 #define CONTROL_PADCONF_GPMC_A3 0x007E
124 #define CONTROL_PADCONF_GPMC_A4 0x0080
125 #define CONTROL_PADCONF_GPMC_A5 0x0082
126 #define CONTROL_PADCONF_GPMC_A6 0x0084
127 #define CONTROL_PADCONF_GPMC_A7 0x0086
128 #define CONTROL_PADCONF_GPMC_A8 0x0088
129 #define CONTROL_PADCONF_GPMC_A9 0x008A
130 #define CONTROL_PADCONF_GPMC_A10 0x008C
131 #define CONTROL_PADCONF_GPMC_A11 0x0264
132 #define CONTROL_PADCONF_GPMC_D0 0x008E
133 #define CONTROL_PADCONF_GPMC_D1 0x0090
134 #define CONTROL_PADCONF_GPMC_D2 0x0092
135 #define CONTROL_PADCONF_GPMC_D3 0x0094
136 #define CONTROL_PADCONF_GPMC_D4 0x0096
137 #define CONTROL_PADCONF_GPMC_D5 0x0098
138 #define CONTROL_PADCONF_GPMC_D6 0x009A
139 #define CONTROL_PADCONF_GPMC_D7 0x009C
140 #define CONTROL_PADCONF_GPMC_D8 0x009E
141 #define CONTROL_PADCONF_GPMC_D9 0x00A0
142 #define CONTROL_PADCONF_GPMC_D10 0x00A2
143 #define CONTROL_PADCONF_GPMC_D11 0x00A4
144 #define CONTROL_PADCONF_GPMC_D12 0x00A6
145 #define CONTROL_PADCONF_GPMC_D13 0x00A8
146 #define CONTROL_PADCONF_GPMC_D14 0x00AA
147 #define CONTROL_PADCONF_GPMC_D15 0x00AC
148 #define CONTROL_PADCONF_GPMC_NCS0 0x00AE
149 #define CONTROL_PADCONF_GPMC_NCS1 0x00B0
150 #define CONTROL_PADCONF_GPMC_NCS2 0x00B2
151 #define CONTROL_PADCONF_GPMC_NCS3 0x00B4
152 #define CONTROL_PADCONF_GPMC_NCS4 0x00B6
153 #define CONTROL_PADCONF_GPMC_NCS5 0x00B8
154 #define CONTROL_PADCONF_GPMC_NCS6 0x00BA
155 #define CONTROL_PADCONF_GPMC_NCS7 0x00BC
156 #define CONTROL_PADCONF_GPMC_CLK 0x00BE
157 #define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0
158 #define CONTROL_PADCONF_GPMC_NOE 0x00C2
159 #define CONTROL_PADCONF_GPMC_NWE 0x00C4
160 #define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6
161 #define CONTROL_PADCONF_GPMC_NBE1 0x00C8
162 #define CONTROL_PADCONF_GPMC_NWP 0x00CA
163 #define CONTROL_PADCONF_GPMC_WAIT0 0x00CC
164 #define CONTROL_PADCONF_GPMC_WAIT1 0x00CE
165 #define CONTROL_PADCONF_GPMC_WAIT2 0x00D0
166 #define CONTROL_PADCONF_GPMC_WAIT3 0x00D2
168 #define CONTROL_PADCONF_DSS_PCLK 0x00D4
169 #define CONTROL_PADCONF_DSS_HSYNC 0x00D6
170 #define CONTROL_PADCONF_DSS_VSYNC 0x00D8
171 #define CONTROL_PADCONF_DSS_ACBIAS 0x00DA
172 #define CONTROL_PADCONF_DSS_DATA0 0x00DC
173 #define CONTROL_PADCONF_DSS_DATA1 0x00DE
174 #define CONTROL_PADCONF_DSS_DATA2 0x00E0
175 #define CONTROL_PADCONF_DSS_DATA3 0x00E2
176 #define CONTROL_PADCONF_DSS_DATA4 0x00E4
177 #define CONTROL_PADCONF_DSS_DATA5 0x00E6
178 #define CONTROL_PADCONF_DSS_DATA6 0x00E8
179 #define CONTROL_PADCONF_DSS_DATA7 0x00EA
180 #define CONTROL_PADCONF_DSS_DATA8 0x00EC
181 #define CONTROL_PADCONF_DSS_DATA9 0x00EE
182 #define CONTROL_PADCONF_DSS_DATA10 0x00F0
183 #define CONTROL_PADCONF_DSS_DATA11 0x00F2
184 #define CONTROL_PADCONF_DSS_DATA12 0x00F4
185 #define CONTROL_PADCONF_DSS_DATA13 0x00F6
186 #define CONTROL_PADCONF_DSS_DATA14 0x00F8
187 #define CONTROL_PADCONF_DSS_DATA15 0x00FA
188 #define CONTROL_PADCONF_DSS_DATA16 0x00FC
189 #define CONTROL_PADCONF_DSS_DATA17 0x00FE
190 #define CONTROL_PADCONF_DSS_DATA18 0x0100
191 #define CONTROL_PADCONF_DSS_DATA19 0x0102
192 #define CONTROL_PADCONF_DSS_DATA20 0x0104
193 #define CONTROL_PADCONF_DSS_DATA21 0x0106
194 #define CONTROL_PADCONF_DSS_DATA22 0x0108
195 #define CONTROL_PADCONF_DSS_DATA23 0x010A
197 #define CONTROL_PADCONF_CAM_HS 0x010C
198 #define CONTROL_PADCONF_CAM_VS 0x010E
199 #define CONTROL_PADCONF_CAM_XCLKA 0x0110
200 #define CONTROL_PADCONF_CAM_PCLK 0x0112
201 #define CONTROL_PADCONF_CAM_FLD 0x0114
202 #define CONTROL_PADCONF_CAM_D0 0x0116
203 #define CONTROL_PADCONF_CAM_D1 0x0118
204 #define CONTROL_PADCONF_CAM_D2 0x011A
205 #define CONTROL_PADCONF_CAM_D3 0x011C
206 #define CONTROL_PADCONF_CAM_D4 0x011E
207 #define CONTROL_PADCONF_CAM_D5 0x0120
208 #define CONTROL_PADCONF_CAM_D6 0x0122
209 #define CONTROL_PADCONF_CAM_D7 0x0124
210 #define CONTROL_PADCONF_CAM_D8 0x0126
211 #define CONTROL_PADCONF_CAM_D9 0x0128
212 #define CONTROL_PADCONF_CAM_D10 0x012A
213 #define CONTROL_PADCONF_CAM_D11 0x012C
214 #define CONTROL_PADCONF_CAM_XCLKB 0x012E
215 #define CONTROL_PADCONF_CAM_WEN 0x0130
216 #define CONTROL_PADCONF_CAM_STROBE 0x0132
217 #define CONTROL_PADCONF_CSI2_DX0 0x0134
218 #define CONTROL_PADCONF_CSI2_DY0 0x0136
219 #define CONTROL_PADCONF_CSI2_DX1 0x0138
220 #define CONTROL_PADCONF_CSI2_DY1 0x013A
222 #define CONTROL_PADCONF_MCBSP2_FSX 0x013C
223 #define CONTROL_PADCONF_MCBSP2_CLKX 0x013E
224 #define CONTROL_PADCONF_MCBSP2_DR 0x0140
225 #define CONTROL_PADCONF_MCBSP2_DX 0x0142
226 #define CONTROL_PADCONF_MMC1_CLK 0x0144
227 #define CONTROL_PADCONF_MMC1_CMD 0x0146
228 #define CONTROL_PADCONF_MMC1_DAT0 0x0148
229 #define CONTROL_PADCONF_MMC1_DAT1 0x014A
230 #define CONTROL_PADCONF_MMC1_DAT2 0x014C
231 #define CONTROL_PADCONF_MMC1_DAT3 0x014E
232 #define CONTROL_PADCONF_MMC1_DAT4 0x0150
233 #define CONTROL_PADCONF_MMC1_DAT5 0x0152
234 #define CONTROL_PADCONF_MMC1_DAT6 0x0154
235 #define CONTROL_PADCONF_MMC1_DAT7 0x0156
237 #define CONTROL_PADCONF_MMC2_CLK 0x0158
238 #define CONTROL_PADCONF_MMC2_CMD 0x015A
239 #define CONTROL_PADCONF_MMC2_DAT0 0x015C
240 #define CONTROL_PADCONF_MMC2_DAT1 0x015E
241 #define CONTROL_PADCONF_MMC2_DAT2 0x0160
242 #define CONTROL_PADCONF_MMC2_DAT3 0x0162
243 #define CONTROL_PADCONF_MMC2_DAT4 0x0164
244 #define CONTROL_PADCONF_MMC2_DAT5 0x0166
245 #define CONTROL_PADCONF_MMC2_DAT6 0x0168
246 #define CONTROL_PADCONF_MMC2_DAT7 0x016A
248 #define CONTROL_PADCONF_MCBSP3_DX 0x016C
249 #define CONTROL_PADCONF_MCBSP3_DR 0x016E
250 #define CONTROL_PADCONF_MCBSP3_CLKX 0x0170
251 #define CONTROL_PADCONF_MCBSP3_FSX 0x0172
252 #define CONTROL_PADCONF_UART2_CTS 0x0174
253 #define CONTROL_PADCONF_UART2_RTS 0x0176
254 #define CONTROL_PADCONF_UART2_TX 0x0178
255 #define CONTROL_PADCONF_UART2_RX 0x017A
257 #define CONTROL_PADCONF_UART1_TX 0x017C
258 #define CONTROL_PADCONF_UART1_RTS 0x017E
259 #define CONTROL_PADCONF_UART1_CTS 0x0180
260 #define CONTROL_PADCONF_UART1_RX 0x0182
261 #define CONTROL_PADCONF_MCBSP4_CLKX 0x0184
262 #define CONTROL_PADCONF_MCBSP4_DR 0x0186
263 #define CONTROL_PADCONF_MCBSP4_DX 0x0188
264 #define CONTROL_PADCONF_MCBSP4_FSX 0x018A
265 #define CONTROL_PADCONF_MCBSP1_CLKR 0x018C
266 #define CONTROL_PADCONF_MCBSP1_FSR 0x018E
267 #define CONTROL_PADCONF_MCBSP1_DX 0x0190
268 #define CONTROL_PADCONF_MCBSP1_DR 0x0192
269 #define CONTROL_PADCONF_MCBSP_CLKS 0x0194
270 #define CONTROL_PADCONF_MCBSP1_FSX 0x0196
271 #define CONTROL_PADCONF_MCBSP1_CLKX 0x0198
273 #define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A
274 #define CONTROL_PADCONF_UART3_RTS_SD 0x019C
275 #define CONTROL_PADCONF_UART3_RX_IRRX 0x019E
276 #define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0
277 #define CONTROL_PADCONF_HSUSB0_CLK 0x01A2
278 #define CONTROL_PADCONF_HSUSB0_STP 0x01A4
279 #define CONTROL_PADCONF_HSUSB0_DIR 0x01A6
280 #define CONTROL_PADCONF_HSUSB0_NXT 0x01A8
281 #define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA
282 #define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC
283 #define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE
284 #define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0
285 #define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2
286 #define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4
287 #define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6
288 #define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8
289 #define CONTROL_PADCONF_I2C1_SCL 0x01BA
290 #define CONTROL_PADCONF_I2C1_SDA 0x01BC
291 #define CONTROL_PADCONF_I2C2_SCL 0x01BE
292 #define CONTROL_PADCONF_I2C2_SDA 0x01C0
293 #define CONTROL_PADCONF_I2C3_SCL 0x01C2
294 #define CONTROL_PADCONF_I2C3_SDA 0x01C4
295 #define CONTROL_PADCONF_I2C4_SCL 0x0A00
296 #define CONTROL_PADCONF_I2C4_SDA 0x0A02
297 #define CONTROL_PADCONF_HDQ_SIO 0x01C6
298 #define CONTROL_PADCONF_MCSPI1_CLK 0x01C8
299 #define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA
300 #define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC
301 #define CONTROL_PADCONF_MCSPI1_CS0 0x01CE
302 #define CONTROL_PADCONF_MCSPI1_CS1 0x01D0
303 #define CONTROL_PADCONF_MCSPI1_CS2 0x01D2
304 #define CONTROL_PADCONF_MCSPI1_CS3 0x01D4
305 #define CONTROL_PADCONF_MCSPI2_CLK 0x01D6
306 #define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8
307 #define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA
308 #define CONTROL_PADCONF_MCSPI2_CS0 0x01DC
309 #define CONTROL_PADCONF_MCSPI2_CS1 0x01DE
311 #define CONTROL_PADCONF_SYS_32K 0x0A04
312 #define CONTROL_PADCONF_SYS_CLKREQ 0x0A06
313 #define CONTROL_PADCONF_SYS_NIRQ 0x01E0
314 #define CONTROL_PADCONF_SYS_BOOT0 0x0A0A
315 #define CONTROL_PADCONF_SYS_BOOT1 0x0A0C
316 #define CONTROL_PADCONF_SYS_BOOT2 0x0A0E
317 #define CONTROL_PADCONF_SYS_BOOT3 0x0A10
318 #define CONTROL_PADCONF_SYS_BOOT4 0x0A12
319 #define CONTROL_PADCONF_SYS_BOOT5 0x0A14
320 #define CONTROL_PADCONF_SYS_BOOT6 0x0A16
321 #define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18
322 #define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A
323 #define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2
324 #define CONTROL_PADCONF_JTAG_NTRST 0x0A1C
325 #define CONTROL_PADCONF_JTAG_TCK 0x0A1E
326 #define CONTROL_PADCONF_JTAG_TMS 0x0A20
327 #define CONTROL_PADCONF_JTAG_TDI 0x0A22
328 #define CONTROL_PADCONF_JTAG_EMU0 0x0A24
329 #define CONTROL_PADCONF_JTAG_EMU1 0x0A26
330 #define CONTROL_PADCONF_ETK_CLK 0x0A28
331 #define CONTROL_PADCONF_ETK_CTL 0x0A2A
332 #define CONTROL_PADCONF_ETK_D0 0x0A2C
333 #define CONTROL_PADCONF_ETK_D1 0x0A2E
334 #define CONTROL_PADCONF_ETK_D2 0x0A30
335 #define CONTROL_PADCONF_ETK_D3 0x0A32
336 #define CONTROL_PADCONF_ETK_D4 0x0A34
337 #define CONTROL_PADCONF_ETK_D5 0x0A36
338 #define CONTROL_PADCONF_ETK_D6 0x0A38
339 #define CONTROL_PADCONF_ETK_D7 0x0A3A
340 #define CONTROL_PADCONF_ETK_D8 0x0A3C
341 #define CONTROL_PADCONF_ETK_D9 0x0A3E
342 #define CONTROL_PADCONF_ETK_D10 0x0A40
343 #define CONTROL_PADCONF_ETK_D11 0x0A42
344 #define CONTROL_PADCONF_ETK_D12 0x0A44
345 #define CONTROL_PADCONF_ETK_D13 0x0A46
346 #define CONTROL_PADCONF_ETK_D14 0x0A48
347 #define CONTROL_PADCONF_ETK_D15 0x0A4A
348 #define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8
349 #define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA
350 #define CONTROL_PADCONF_ETK_D0_ES2 0x05DC
351 #define CONTROL_PADCONF_ETK_D1_ES2 0x05DE
352 #define CONTROL_PADCONF_ETK_D2_ES2 0x05E0
353 #define CONTROL_PADCONF_ETK_D3_ES2 0x05E2
354 #define CONTROL_PADCONF_ETK_D4_ES2 0x05E4
355 #define CONTROL_PADCONF_ETK_D5_ES2 0x05E6
356 #define CONTROL_PADCONF_ETK_D6_ES2 0x05E8
357 #define CONTROL_PADCONF_ETK_D7_ES2 0x05EA
358 #define CONTROL_PADCONF_ETK_D8_ES2 0x05EC
359 #define CONTROL_PADCONF_ETK_D9_ES2 0x05EE
360 #define CONTROL_PADCONF_ETK_D10_ES2 0x05F0
361 #define CONTROL_PADCONF_ETK_D11_ES2 0x05F2
362 #define CONTROL_PADCONF_ETK_D12_ES2 0x05F4
363 #define CONTROL_PADCONF_ETK_D13_ES2 0x05F6
364 #define CONTROL_PADCONF_ETK_D14_ES2 0x05F8
365 #define CONTROL_PADCONF_ETK_D15_ES2 0x05FA
366 #define CONTROL_PADCONF_JTAG_RTCK 0x0A4E
367 #define CONTROL_PADCONF_JTAG_TDO 0x0A50
369 #define CONTROL_PADCONF_D2D_MCAD0 0x01E4
370 #define CONTROL_PADCONF_D2D_MCAD1 0x01E6
371 #define CONTROL_PADCONF_D2D_MCAD2 0x01E8
372 #define CONTROL_PADCONF_D2D_MCAD3 0x01EA
373 #define CONTROL_PADCONF_D2D_MCAD4 0x01EC
374 #define CONTROL_PADCONF_D2D_MCAD5 0x01EE
375 #define CONTROL_PADCONF_D2D_MCAD6 0x01F0
376 #define CONTROL_PADCONF_D2D_MCAD7 0x01F2
377 #define CONTROL_PADCONF_D2D_MCAD8 0x01F4
378 #define CONTROL_PADCONF_D2D_MCAD9 0x01F6
379 #define CONTROL_PADCONF_D2D_MCAD10 0x01F8
380 #define CONTROL_PADCONF_D2D_MCAD11 0x01FA
381 #define CONTROL_PADCONF_D2D_MCAD12 0x01FC
382 #define CONTROL_PADCONF_D2D_MCAD13 0x01FE
383 #define CONTROL_PADCONF_D2D_MCAD14 0x0200
384 #define CONTROL_PADCONF_D2D_MCAD15 0x0202
385 #define CONTROL_PADCONF_D2D_MCAD16 0x0204
386 #define CONTROL_PADCONF_D2D_MCAD17 0x0206
387 #define CONTROL_PADCONF_D2D_MCAD18 0x0208
388 #define CONTROL_PADCONF_D2D_MCAD19 0x020A
389 #define CONTROL_PADCONF_D2D_MCAD20 0x020C
390 #define CONTROL_PADCONF_D2D_MCAD21 0x020E
391 #define CONTROL_PADCONF_D2D_MCAD22 0x0210
392 #define CONTROL_PADCONF_D2D_MCAD23 0x0212
393 #define CONTROL_PADCONF_D2D_MCAD24 0x0214
394 #define CONTROL_PADCONF_D2D_MCAD25 0x0216
395 #define CONTROL_PADCONF_D2D_MCAD26 0x0218
396 #define CONTROL_PADCONF_D2D_MCAD27 0x021A
397 #define CONTROL_PADCONF_D2D_MCAD28 0x021C
398 #define CONTROL_PADCONF_D2D_MCAD29 0x021E
399 #define CONTROL_PADCONF_D2D_MCAD30 0x0220
400 #define CONTROL_PADCONF_D2D_MCAD31 0x0222
401 #define CONTROL_PADCONF_D2D_MCAD32 0x0224
402 #define CONTROL_PADCONF_D2D_MCAD33 0x0226
403 #define CONTROL_PADCONF_D2D_MCAD34 0x0228
404 #define CONTROL_PADCONF_D2D_MCAD35 0x022A
405 #define CONTROL_PADCONF_D2D_MCAD36 0x022C
406 #define CONTROL_PADCONF_D2D_CLK26MI 0x022E
407 #define CONTROL_PADCONF_D2D_NRESPWRON 0x0230
408 #define CONTROL_PADCONF_D2D_NRESWARM 0x0232
409 #define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234
410 #define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236
411 #define CONTROL_PADCONF_D2D_SPINT 0x0238
412 #define CONTROL_PADCONF_D2D_FRINT 0x023A
413 #define CONTROL_PADCONF_D2D_DMAREQ0 0x023C
414 #define CONTROL_PADCONF_D2D_DMAREQ1 0x023E
415 #define CONTROL_PADCONF_D2D_DMAREQ2 0x0240
416 #define CONTROL_PADCONF_D2D_DMAREQ3 0x0242
417 #define CONTROL_PADCONF_D2D_N3GTRST 0x0244
418 #define CONTROL_PADCONF_D2D_N3GTDI 0x0246
419 #define CONTROL_PADCONF_D2D_N3GTDO 0x0248
420 #define CONTROL_PADCONF_D2D_N3GTMS 0x024A
421 #define CONTROL_PADCONF_D2D_N3GTCK 0x024C
422 #define CONTROL_PADCONF_D2D_N3GRTCK 0x024E
423 #define CONTROL_PADCONF_D2D_MSTDBY 0x0250
424 #define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C
425 #define CONTROL_PADCONF_D2D_IDLEREQ 0x0252
426 #define CONTROL_PADCONF_D2D_IDLEACK 0x0254
427 #define CONTROL_PADCONF_D2D_MWRITE 0x0256
428 #define CONTROL_PADCONF_D2D_SWRITE 0x0258
429 #define CONTROL_PADCONF_D2D_MREAD 0x025A
430 #define CONTROL_PADCONF_D2D_SREAD 0x025C
431 #define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E
432 #define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260
433 #define CONTROL_PADCONF_SDRC_CKE0 0x0262
434 #define CONTROL_PADCONF_SDRC_CKE1 0x0264
437 #define CONTROL_PADCONF_SYS_NRESWARM 0x0A08
439 #define CONTROL_PADCONF_CCDC_PCLK 0x01E4
440 #define CONTROL_PADCONF_CCDC_FIELD 0x01E6
441 #define CONTROL_PADCONF_CCDC_HD 0x01E8
442 #define CONTROL_PADCONF_CCDC_VD 0x01EA
443 #define CONTROL_PADCONF_CCDC_WEN 0x01EC
444 #define CONTROL_PADCONF_CCDC_DATA0 0x01EE
445 #define CONTROL_PADCONF_CCDC_DATA1 0x01F0
446 #define CONTROL_PADCONF_CCDC_DATA2 0x01F2
447 #define CONTROL_PADCONF_CCDC_DATA3 0x01F4
448 #define CONTROL_PADCONF_CCDC_DATA4 0x01F6
449 #define CONTROL_PADCONF_CCDC_DATA5 0x01F8
450 #define CONTROL_PADCONF_CCDC_DATA6 0x01FA
451 #define CONTROL_PADCONF_CCDC_DATA7 0x01FC
453 #define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE
454 #define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200
455 #define CONTROL_PADCONF_RMII_RXD0 0x0202
456 #define CONTROL_PADCONF_RMII_RXD1 0x0204
457 #define CONTROL_PADCONF_RMII_CRS_DV 0x0206
458 #define CONTROL_PADCONF_RMII_RXER 0x0208
459 #define CONTROL_PADCONF_RMII_TXD0 0x020A
460 #define CONTROL_PADCONF_RMII_TXD1 0x020C
461 #define CONTROL_PADCONF_RMII_TXEN 0x020E
462 #define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210
463 #define CONTROL_PADCONF_USB0_DRVBUS 0x0212
465 #define CONTROL_PADCONF_HECC1_TXD 0x0214
466 #define CONTROL_PADCONF_HECC1_RXD 0x0216
468 #define CONTROL_PADCONF_SYS_BOOT7 0x0218
469 #define CONTROL_PADCONF_SDRC_DQS0N 0x021A
470 #define CONTROL_PADCONF_SDRC_DQS1N 0x021C
471 #define CONTROL_PADCONF_SDRC_DQS2N 0x021E
472 #define CONTROL_PADCONF_SDRC_DQS3N 0x0220
473 #define CONTROL_PADCONF_STRBEN_DLY0 0x0222
474 #define CONTROL_PADCONF_STRBEN_DLY1 0x0224
475 #define CONTROL_PADCONF_SYS_BOOT8 0x0226
478 #define CONTROL_PADCONF_GPIO112 0x0134
479 #define CONTROL_PADCONF_GPIO113 0x0136
480 #define CONTROL_PADCONF_GPIO114 0x0138
481 #define CONTROL_PADCONF_GPIO115 0x013A
482 #define CONTROL_PADCONF_GPIO127 0x0A54
483 #define CONTROL_PADCONF_GPIO126 0x0A56
484 #define CONTROL_PADCONF_GPIO128 0x0A58
485 #define CONTROL_PADCONF_GPIO129 0x0A5A
489 #define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C)