Lines Matching +full:6 +full:- +full:3
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2006-2008
5 * Richard Woodruff <r-woodruff2@ti.com>
19 IP_SDR = 3,
38 * counter is a result of ( tREFI / tCK ) - 50.
41 #define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
42 #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
43 #define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
52 /* rkw - need to find of 90/72 degree recommendation for speed like before */
53 #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
63 #define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */
94 #define V_MCFG_DEEPPD_EN (0x1 << 3)
96 #define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */
99 #define V_MCFG_CASWIDTH(caswidth) (((caswidth)-5) << 20) /* 20:22 */
101 #define V_MCFG_RASWIDTH(raswidth) (((raswidth)-11) << 24) /* 24:26 */
111 #define HYNIX_TDAL_165 6
112 #define HYNIX_TDPL_165 3
114 #define HYNIX_TRCD_165 3
115 #define HYNIX_TRP_165 3
137 #define HYNIX_TDAL_200 6
138 #define HYNIX_TDPL_200 3
141 #define HYNIX_TRP_200 3
163 #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
164 /* 15/6 + 18/6 = 5.5 -> 6 */
165 #define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
166 #define INFINEON_TRRD_165 2 /* 12/6 = 2 */
167 #define INFINEON_TRCD_165 3 /* 18/6 = 3 */
168 #define INFINEON_TRP_165 3 /* 18/6 = 3 */
169 #define INFINEON_TRAS_165 7 /* 42/6 = 7 */
170 #define INFINEON_TRC_165 10 /* 60/6 = 10 */
171 #define INFINEON_TRFC_165 12 /* 72/6 = 12 */
182 #define INFINEON_XSR_165 20 /* 120/6 = 20 */
189 #define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */
190 /* 15/6 + 18/6 = 5.5 -> 6 */
191 #define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
192 #define MICRON_TRRD_165 2 /* 12/6 = 2 */
193 #define MICRON_TRCD_165 3 /* 18/6 = 3 */
194 #define MICRON_TRP_165 3 /* 18/6 = 3 */
195 #define MICRON_TRAS_165 7 /* 42/6 = 7 */
196 #define MICRON_TRC_165 10 /* 60/6 = 10 */
197 #define MICRON_TRFC_165 21 /* 125/6 = 21 */
207 #define MICRON_XSR_165 23 /* 138/6 = 23 */
208 #define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */
222 (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
226 #define MICRON_TDAL_200 6
227 #define MICRON_TDPL_200 3
229 #define MICRON_TRCD_200 3
230 #define MICRON_TRP_200 3
251 /* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
255 #define SAMSUNG_TRCD_165 3
256 #define SAMSUNG_TRP_165 3
289 (SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \
295 #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
296 /* 15/6 + 18/6 = 5.5 -> 6 */
297 #define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
298 #define NUMONYX_TRRD_165 2 /* 12/6 = 2 */
299 #define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */
300 #define NUMONYX_TRP_165 3 /* 18/6 = 3 */
301 #define NUMONYX_TRAS_165 7 /* 42/6 = 7 */
302 #define NUMONYX_TRC_165 10 /* 60/6 = 10 */
303 #define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */
313 #define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */
314 #define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */
324 #define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck */
325 /* 15/5 + 15/5 = 3 + 3 -> 6 */
326 #define NUMONYX_TDPL_200 3 /* 15/5 = 3 -> 3 (Twr) */
328 #define NUMONYX_TRCD_200 4 /* 16.2/5 = 3.24 -> 4 */
329 #define NUMONYX_TRP_200 3 /* 15/5 = 3 */
342 #define NUMONYX_TXP_200 3
353 * GPMC settings -
357 * PART is the part name e.g. STNOR - Intel Strata Flash
358 * x is GPMC config registers from 1 to 6 (there will be 6 macros)
364 * go into corresponding mem-boardName.h file
367 * STNOR - Intel Strata Flash
368 * SMNAND - Samsung NAND
369 * MPDB - H4 MPDB board
370 * SBNOR - Sibley NOR
371 * MNAND - Micron Large page x16 NAND
372 * ONNAND - Samsung One NAND
374 * include/configs/file.h contains the defn - for all CS we are interested
379 * x - CS number
380 * PART - Part Name as defined above
381 * SIZE - how big is the mapping to be
382 * GPMC_SIZE_128M - 0x8
383 * GPMC_SIZE_64M - 0xC
384 * GPMC_SIZE_32M - 0xE
385 * GPMC_SIZE_16M - 0xF
386 * MAP - Map this CS to which address(GPMC address space)- Absolute address
472 #define DBG_MPDB 6