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42 #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
63 #define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */
96 #define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */
111 #define HYNIX_TDAL_165 6
137 #define HYNIX_TDAL_200 6
163 #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
164 /* 15/6 + 18/6 = 5.5 -> 6 */
165 #define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
166 #define INFINEON_TRRD_165 2 /* 12/6 = 2 */
167 #define INFINEON_TRCD_165 3 /* 18/6 = 3 */
168 #define INFINEON_TRP_165 3 /* 18/6 = 3 */
169 #define INFINEON_TRAS_165 7 /* 42/6 = 7 */
170 #define INFINEON_TRC_165 10 /* 60/6 = 10 */
171 #define INFINEON_TRFC_165 12 /* 72/6 = 12 */
182 #define INFINEON_XSR_165 20 /* 120/6 = 20 */
189 #define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */
190 /* 15/6 + 18/6 = 5.5 -> 6 */
191 #define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
192 #define MICRON_TRRD_165 2 /* 12/6 = 2 */
193 #define MICRON_TRCD_165 3 /* 18/6 = 3 */
194 #define MICRON_TRP_165 3 /* 18/6 = 3 */
195 #define MICRON_TRAS_165 7 /* 42/6 = 7 */
196 #define MICRON_TRC_165 10 /* 60/6 = 10 */
197 #define MICRON_TRFC_165 21 /* 125/6 = 21 */
207 #define MICRON_XSR_165 23 /* 138/6 = 23 */
208 #define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */
226 #define MICRON_TDAL_200 6
295 #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
296 /* 15/6 + 18/6 = 5.5 -> 6 */
297 #define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
298 #define NUMONYX_TRRD_165 2 /* 12/6 = 2 */
299 #define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */
300 #define NUMONYX_TRP_165 3 /* 18/6 = 3 */
301 #define NUMONYX_TRAS_165 7 /* 42/6 = 7 */
302 #define NUMONYX_TRC_165 10 /* 60/6 = 10 */
303 #define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */
313 #define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */
324 #define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck */
325 /* 15/5 + 15/5 = 3 + 3 -> 6 */
358 * x is GPMC config registers from 1 to 6 (there will be 6 macros)
472 #define DBG_MPDB 6