Lines Matching refs:AIPS0_BASE

32 #define AIPS0_BASE			(0x41000000UL)  macro
129 #define IOMUXC0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT)))
131 #define WDG0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * WDG0_AIPS0_SLOT)))
134 #define SCG0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * SCG0_AIPS0_SLOT)))
136 #define PCC0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * PCC0_AIPS0_SLOT)))
140 #define IOMUXC0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT)))
155 #define LPI2C1_BASE_ADDR	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C0_AIPS0_SLOT)))
156 #define LPI2C2_BASE_ADDR	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C1_AIPS0_SLOT)))
157 #define LPI2C3_BASE_ADDR	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C2_AIPS0_SLOT)))
158 #define LPI2C4_BASE_ADDR	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C3_AIPS0_SLOT)))
164 #define LPUART0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART0_AIPS0_SLOT)))
165 #define LPUART1_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART1_AIPS0_SLOT)))
176 #define RGPIO2P0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT)))