Lines Matching +full:0 +full:x2f000000
11 #define CAAM_SEC_SRAM_BASE (0x26000000)
15 #define OCRAM_0_BASE (0x2F000000)
19 #define OCRAM_1_BASE (0x2F020000)
23 #define TCML_BASE (0x1FFD0000)
24 #define TCMU_BASE (0x20000000)
26 #define AIPS3_BASE (0x40800000UL)
28 #define AIPS2_BASE (0x40000000UL)
30 #define AIPS1_BASE (0x41080000UL)
32 #define AIPS0_BASE (0x41000000UL)
87 #define CORE_B_ROM_BASE (0x00000000)
94 #define IOMUXC_PCR_MUX_ALT0 (0<<8)
111 #define IOMUXC_PSMI_IMUX_ALT0 (0x0)
112 #define IOMUXC_PSMI_IMUX_ALT1 (0x1)
113 #define IOMUXC_PSMI_IMUX_ALT2 (0x2)
114 #define IOMUXC_PSMI_IMUX_ALT3 (0x3)
115 #define IOMUXC_PSMI_IMUX_ALT4 (0x4)
116 #define IOMUXC_PSMI_IMUX_ALT5 (0x5)
117 #define IOMUXC_PSMI_IMUX_ALT6 (0x6)
118 #define IOMUXC_PSMI_IMUX_ALT7 (0x7)
123 #define SIM_SOPT1_A7_SW_RESET (1<<0)
126 #define IOMUXC_PCR_MUX_ALT_MASK (0xF00)
127 #define IOMUXC_PSMI_IMUX_ALT_SHIFT (0)
141 #define PSMI0_RBASE ((IOMUXC0_RBASE + 0x100)) /* in iomuxc0 after pta and ptb */
181 #define CMC0_SRS (CMC0_RBASE + 0x20)
182 #define CMC0_SSRS (CMC0_RBASE + 0x28)
183 #define CMC1_SRS (CMC1_RBASE + 0x20)
184 #define CMC1_SSRS (CMC1_RBASE + 0x28)
186 #define IOMUXC0_PCR0 (IOMUXC0_RBASE + (4 * 0))
194 #define SCG_CSR (SCG0_RBASE + 0x010)
195 #define SCG_RCCR (SCG0_RBASE + 0x014)
196 #define SCG_VCCR (SCG0_RBASE + 0x018)
197 #define SCG_HCCR (SCG0_RBASE + 0x01c)
225 #define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0)))
260 #define RGPIO2P_GPIO2_BASE_ADDR (RGPIO2P0_RBASE + 0x40)
262 #define RGPIO2P_GPIO4_BASE_ADDR (RGPIO2P1_RBASE + 0x40)
263 #define RGPIO2P_GPIO5_BASE_ADDR (RGPIO2P1_RBASE + 0x80)
264 #define RGPIO2P_GPIO6_BASE_ADDR (RGPIO2P1_RBASE + 0xc0)
267 #define MMDC_MDCTL_OFFSET (0x000)
268 #define MMDC_MDPDC_OFFSET (0x004)
269 #define MMDC_MDOTC_OFFSET (0x008)
270 #define MMDC_MDCFG0_OFFSET (0x00C)
271 #define MMDC_MDCFG1_OFFSET (0x010)
272 #define MMDC_MDCFG2_OFFSET (0x014)
273 #define MMDC_MDMISC_OFFSET (0x018)
274 #define MMDC_MDSCR_OFFSET (0x01C)
275 #define MMDC_MDREF_OFFSET (0x020)
276 #define MMDC_MDRWD_OFFSET (0x02C)
277 #define MMDC_MDOR_OFFSET (0x030)
278 #define MMDC_MDMRR_OFFSET (0x034)
279 #define MMDC_MDCFG3LP_OFFSET (0x038)
280 #define MMDC_MDMR4_OFFSET (0x03C)
281 #define MMDC_MDASP_OFFSET (0x040)
283 #define MMDC_MAARCR_OFFSET (0x400)
284 #define MMDC_MAPSR_OFFSET (0x404)
285 #define MMDC_MAEXIDR0_OFFSET (0x408)
286 #define MMDC_MAEXIDR1_OFFSET (0x40C)
287 #define MMDC_MADPCR0_OFFSET (0x410)
288 #define MMDC_MADPCR1_OFFSET (0x414)
289 #define MMDC_MADPSR0_OFFSET (0x418)
290 #define MMDC_MADPSR1_OFFSET (0x41C)
291 #define MMDC_MADPSR2_OFFSET (0x420)
292 #define MMDC_MADPSR3_OFFSET (0x424)
293 #define MMDC_MADPSR4_OFFSET (0x428)
294 #define MMDC_MADPSR5_OFFSET (0x42C)
295 #define MMDC_MASBS0_OFFSET (0x430)
296 #define MMDC_MASBS1_OFFSET (0x434)
297 #define MMDC_MAGENP_OFFSET (0x440)
299 #define MMDC_MPZQHWCTRL_OFFSET (0x800)
300 #define MMDC_MPZQSWCTRL_OFFSET (0x804)
301 #define MMDC_MPWLGCR_OFFSET (0x808)
302 #define MMDC_MPWLDECTRL0_OFFSET (0x80C)
303 #define MMDC_MPWLDECTRL1_OFFSET (0x810)
304 #define MMDC_MPWLDLST_OFFSET (0x814)
305 #define MMDC_MPODTCTRL_OFFSET (0x818)
306 #define MMDC_MPREDQBY0DL_OFFSET (0x81C)
307 #define MMDC_MPREDQBY1DL_OFFSET (0x820)
308 #define MMDC_MPREDQBY2DL_OFFSET (0x824)
309 #define MMDC_MPREDQBY3DL_OFFSET (0x828)
310 #define MMDC_MPWRDQBY0DL_OFFSET (0x82C)
311 #define MMDC_MPWRDQBY1DL_OFFSET (0x830)
312 #define MMDC_MPWRDQBY2DL_OFFSET (0x834)
313 #define MMDC_MPWRDQBY3DL_OFFSET (0x838)
314 #define MMDC_MPDGCTRL0_OFFSET (0x83C)
315 #define MMDC_MPDGCTRL1_OFFSET (0x840)
316 #define MMDC_MPDGDLST_OFFSET (0x844)
317 #define MMDC_MPRDDLCTL_OFFSET (0x848)
318 #define MMDC_MPRDDLST_OFFSET (0x84C)
319 #define MMDC_MPWRDLCTL_OFFSET (0x850)
320 #define MMDC_MPWRDLST_OFFSET (0x854)
321 #define MMDC_MPSDCTRL_OFFSET (0x858)
322 #define MMDC_MPZQLP2CTL_OFFSET (0x85C)
323 #define MMDC_MPRDDLHWCTL_OFFSET (0x860)
324 #define MMDC_MPWRDLHWCTL_OFFSET (0x864)
325 #define MMDC_MPRDDLHWST0_OFFSET (0x868)
326 #define MMDC_MPRDDLHWST1_OFFSET (0x86C)
327 #define MMDC_MPWRDLHWST0_OFFSET (0x870)
328 #define MMDC_MPWRDLHWST1_OFFSET (0x874)
329 #define MMDC_MPWLHWERR_OFFSET (0x878)
330 #define MMDC_MPDGHWST0_OFFSET (0x87C)
331 #define MMDC_MPDGHWST1_OFFSET (0x880)
332 #define MMDC_MPDGHWST2_OFFSET (0x884)
333 #define MMDC_MPDGHWST3_OFFSET (0x888)
334 #define MMDC_MPPDCMPR1_OFFSET (0x88C)
335 #define MMDC_MPPDCMPR2_OFFSET (0x890)
336 #define MMDC_MPSWDAR_OFFSET (0x894)
337 #define MMDC_MPSWDRDR0_OFFSET (0x898)
338 #define MMDC_MPSWDRDR1_OFFSET (0x89C)
339 #define MMDC_MPSWDRDR2_OFFSET (0x8A0)
340 #define MMDC_MPSWDRDR3_OFFSET (0x8A4)
341 #define MMDC_MPSWDRDR4_OFFSET (0x8A8)
342 #define MMDC_MPSWDRDR5_OFFSET (0x8AC)
343 #define MMDC_MPSWDRDR6_OFFSET (0x8B0)
344 #define MMDC_MPSWDRDR7_OFFSET (0x8B4)
345 #define MMDC_MPMUR_OFFSET (0x8B8)
346 #define MMDC_MPWRCADL_OFFSET (0x8BC)
347 #define MMDC_MPDCCR_OFFSET (0x8C0)
348 #define MMDC_MPBC_OFFSET (0x8C4)
349 #define MMDC_MPSWDRAR_OFFSET (0x8C8)
352 #define MMDC_IPS_ILL_ADDR_START_OFFSET (0x8CC)
478 #define MMDC_MDSCR_CMD_BA (0)
482 #define MMDC_MPZQHWCTRL_ZQ_MODE (0)
491 #define MMDC_MPZQSWCTRL_ZQ_SW_FOR (0)
503 #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR (0)
508 #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR (0)
517 #define MMDC_MPSWDAR_SW_DUMMY_WR (0)
524 #define MMDC_MASBS1_SBS_VLD (0)
531 #define MMDC_MDREF_START_REF (0)
534 #define MMDC_MPWLGCR_HW_WL_EN (0)
537 #define MMDC_MPBC_BIST_DM_LP_EN (0)
551 #define MMDC_MPODTCTRL_ODT_WR_PAS_EN (0)
565 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT (0)
571 #define MMDC_MDCFG3LP_tRPab_LP (0)
576 #define MMDC_MDOR_RST_to_CKE (0)
584 #define MMDC_MDCFG0_tCL (0)
594 #define MMDC_MDCFG1_tCWL (0)
600 #define MMDC_MDCFG2_tRRD (0)
608 #define MMDC_MDRWD_RTR_DIFF (0)
619 #define MMDC_MDPDC_tCKSRE (0)
622 #define MMDC_MDASP_CS0_END (0)
626 #define MMDC_MAEXIDR0_EXC_ID_MONITOR0 (0)
630 #define MMDC_MAEXIDR1_EXC_ID_MONITOR2 (0)
636 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0 (0)
642 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0 (0)
653 #define MMDC_MPWRDQBY0DL_WR_DQ0_DEL (0)
664 #define MMDC_MPWRDQBY1DL_WR_DQ8_DEL (0)
675 #define MMDC_MPWRDQBY2DL_WR_DQ16_DEL (0)
686 #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL (0)
689 #define MMDC_MDCTL_SDE_0_MASK ((0x1 << MMDC_MDCTL_SDE_0))
690 #define MMDC_MDCTL_SDE_1_MASK ((0x1 << MMDC_MDCTL_SDE_1))
691 #define MMDC_MDCTL_BL_MASK ((0x1 << MMDC_MDCTL_BL))
692 #define MMDC_MDCTL_ROW_MASK ((0x7 << MMDC_MDCTL_ROW))
693 #define MMDC_MDCTL_COL_MASK ((0x7 << MMDC_MDCTL_COL))
694 #define MMDC_MDCTL_DSIZ_MASK ((0x3 << MMDC_MDCTL_DSIZ))
697 #define MMDC_MDMISC_CS0_RDY_MASK ((0x1 << MMDC_MDMISC_CS0_RDY))
698 #define MMDC_MDMISC_CS1_RDY_MASK ((0x1 << MMDC_MDMISC_CS1_RDY))
699 #define MMDC_MDMISC_CK1_DEL_MASK ((0x3 << MMDC_MDMISC_CK1_DEL))
700 #define MMDC_MDMISC_CK1_GATING_MASK ((0x1 << MMDC_MDMISC_CK1_GATING))
701 #define MMDC_MDMISC_CALIB_PER_CS_MASK ((0x1 << MMDC_MDMISC_CALIB_PER_CS))
702 #define MMDC_MDMISC_ADDR_MIRROR_MASK ((0x1 << MMDC_MDMISC_ADDR_MIRROR))
703 #define MMDC_MDMISC_LHD_MASK ((0x1 << MMDC_MDMISC_LHD))
704 #define MMDC_MDMISC_WALAT_MASK ((0x3 << MMDC_MDMISC_WALAT))
705 #define MMDC_MDMISC_BI_MASK ((0x1 << MMDC_MDMISC_BI))
706 #define MMDC_MDMISC_LPDDR2_S_MASK ((0x1 << MMDC_MDMISC_LPDDR2_S))
707 #define MMDC_MDMISC_MIF3_MODE_MASK ((0x3 << MMDC_MDMISC_MIF3_MODE))
708 #define MMDC_MDMISC_RALAT_MASK ((0x7 << MMDC_MDMISC_RALAT))
709 #define MMDC_MDMISC_DDR_4_BANK_MASK ((0x1 << MMDC_MDMISC_DDR_4_BANK))
710 #define MMDC_MDMISC_DDR_TYPE_MASK ((0x3 << MMDC_MDMISC_DDR_TYPE))
711 #define MMDC_MDMISC_RST_MASK ((0x1 << MMDC_MDMISC_RST))
714 #define MMDC_MPWLGCR_WL_HW_ERR_MASK ((0xf << MMDC_MPWLGCR_WL_HW_ERR))
717 #define MMDC_MDSCR_CMD_ADDR_MSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_MSB))
718 #define MMDC_MDSCR_MR_OP_MASK ((0xff << MMDC_MDSCR_MR_OP))
719 #define MMDC_MDSCR_CMD_ADDR_LSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_LSB))
720 #define MMDC_MDSCR_MR_ADDR_MASK ((0xff << MMDC_MDSCR_MR_ADDR))
721 #define MMDC_MDSCR_CON_REQ_MASK ((0x1 << MMDC_MDSCR_CON_REQ))
722 #define MMDC_MDSCR_CON_ACK_MASK ((0x1 << MMDC_MDSCR_CON_ACK))
723 #define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK ((0x1 << MMDC_MDSCR_MRR_READ_DATA_VALID))
724 #define MMDC_MDSCR_WL_EN_MASK ((0x1 << MMDC_MDSCR_WL_EN))
725 #define MMDC_MDSCR_CMD_MASK ((0x7 << MMDC_MDSCR_CMD))
726 #define MMDC_MDSCR_CMD_CS_MASK ((0x1 << MMDC_MDSCR_CMD_CS))
727 #define MMDC_MDSCR_CMD_BA_MASK ((0x7 << MMDC_MDSCR_CMD_BA))
730 #define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK ((0x1 << MMDC_MPZQHWCTRL_ZQ_HW_FOR))
731 #define MMDC_MPZQHWCTRL_ZQ_MODE_MASK ((0x3 << MMDC_MPZQHWCTRL_ZQ_MODE))
734 #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK ((0x3 << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP))
735 #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK ((0x1 << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL))
736 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_PD))
737 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL))
738 #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL))
739 #define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_RES))
740 #define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_FOR))
743 #define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK ((0x1 << MMDC_MPDGCTRL0_RST_RD_FIFO))
744 #define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK ((0x1 << MMDC_MPDGCTRL0_DG_CMP_CYC))
745 #define MMDC_MPDGCTRL0_DG_DIS_MASK ((0x1 << MMDC_MPDGCTRL0_DG_DIS))
746 #define MMDC_MPDGCTRL0_HW_DG_EN_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_EN))
747 #define MMDC_MPDGCTRL0_HW_DG_ERR_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_ERR))
750 #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC))
751 #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_EN))
752 #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR_MASK ((0xf << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR))
755 #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC))
756 #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_EN))
757 #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR_MASK ((0xf << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR))
760 #define MMDC_MPSWDAR_TEST_DUMMY_EN_MASK ((0x1 << MMDC_MPSWDAR_TEST_DUMMY_EN))
761 #define MMDC_MPSWDAR_SW_DUM_CMP3_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP3))
762 #define MMDC_MPSWDAR_SW_DUM_CMP2_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP2))
763 #define MMDC_MPSWDAR_SW_DUM_CMP1_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP1))
764 #define MMDC_MPSWDAR_SW_DUM_CMP0_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP0))
765 #define MMDC_MPSWDAR_SW_DUMMY_RD_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_RD))
766 #define MMDC_MPSWDAR_SW_DUMMY_WR_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_WR))
769 #define MMDC_MADPCR0_SBS_MASK ((0x1 << MMDC_MADPCR0_SBS))
770 #define MMDC_MADPCR0_SBS_EN_MASK ((0x1 << MMDC_MADPCR0_SBS_EN))
773 #define MMDC_MASBS1_SBS_VLD_MASK ((0x1 << MMDC_MASBS1_SBS_VLD))
774 #define MMDC_MASBS1_SBS_TYPE_MASK ((0x1 << MMDC_MASBS1_SBS_TYPE))
777 #define MMDC_MDREF_REF_CNT_MASK ((0xffff << MMDC_MDREF_REF_CNT))
778 #define MMDC_MDREF_REF_SEL_MASK ((0x3 << MMDC_MDREF_REF_SEL))
779 #define MMDC_MDREF_REFR_MASK ((0x7 << MMDC_MDREF_REFR))
780 #define MMDC_MDREF_START_REF_MASK ((0x1 << MMDC_MDREF_START_REF))
783 #define MMDC_MPWLGCR_HW_WL_EN_MASK ((0x1 << MMDC_MPWLGCR_HW_WL_EN))
786 #define MMDC_MPBC_BIST_DM_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DM_LP_EN))
787 #define MMDC_MPBC_BIST_CA0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_CA0_LP_EN))
788 #define MMDC_MPBC_BIST_DQ0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ0_LP_EN))
789 #define MMDC_MPBC_BIST_DQ1_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ1_LP_EN))
790 #define MMDC_MPBC_BIST_DQ2_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ2_LP_EN))
791 #define MMDC_MPBC_BIST_DQ3_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ3_LP_EN))
792 #define MMDC_MPBC_BIST_DQ_LP_EN_MASK ((0xf << MMDC_MPBC_BIST_DQ0_LP_EN))
795 #define MMDC_MPMUR_FRC_MSR_MASK ((0x1 << MMDC_MPMUR_FRC_MSR))
798 #define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_ACT_EN))
799 #define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_PAS_EN))
800 #define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_ACT_EN))
801 #define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_PAS_EN))
804 #define MMDC_MAPSR_DVACK_MASK ((0x1 << MMDC_MAPSR_DVACK))
805 #define MMDC_MAPSR_LPACK_MASK ((0x1 << MMDC_MAPSR_LPACK))
806 #define MMDC_MAPSR_DVFS_MASK ((0x1 << MMDC_MAPSR_DVFS))
807 #define MMDC_MAPSR_LPMD_MASK ((0x1 << MMDC_MAPSR_LPMD))
810 #define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK ((0x1 << MMDC_MAARCR_ARCR_EXC_ERR_EN))
813 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK ((0x7f << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS))
814 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK ((0xff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL))
815 #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK ((0x1ff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT))
818 #define MMDC_MDCFG3LP_tRC_LP_MASK ((0x3f << MMDC_MDCFG3LP_tRC_LP))
819 #define MMDC_MDCFG3LP_tRCD_LP_MASK ((0xf << MMDC_MDCFG3LP_tRCD_LP))
820 #define MMDC_MDCFG3LP_tRPpb_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPpb_LP))
821 #define MMDC_MDCFG3LP_tRPab_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPab_LP))
824 #define MMDC_MDOR_tXPR_MASK ((0xff << MMDC_MDOR_tXPR))
825 #define MMDC_MDOR_SDE_to_RST_MASK ((0x3f << MMDC_MDOR_SDE_to_RST))
826 #define MMDC_MDOR_RST_to_CKE_MASK ((0x3f << MMDC_MDOR_RST_to_CKE))
829 #define MMDC_MDCFG0_tRFC_MASK ((0xff << MMDC_MDCFG0_tRFC))
830 #define MMDC_MDCFG0_tXS_MASK ((0xff << MMDC_MDCFG0_tXS))
831 #define MMDC_MDCFG0_tXP_MASK ((0x7 << MMDC_MDCFG0_tXP))
832 #define MMDC_MDCFG0_tXPDLL_MASK ((0xf << MMDC_MDCFG0_tXPDLL))
833 #define MMDC_MDCFG0_tFAW_MASK ((0x1f << MMDC_MDCFG0_tFAW))
834 #define MMDC_MDCFG0_tCL_MASK ((0xf << MMDC_MDCFG0_tCL))
837 #define MMDC_MDCFG1_tRCD_MASK ((0x7 << MMDC_MDCFG1_tRCD))
838 #define MMDC_MDCFG1_tRP_MASK ((0x7 << MMDC_MDCFG1_tRP))
839 #define MMDC_MDCFG1_tRC_MASK ((0x1f << MMDC_MDCFG1_tRC))
840 #define MMDC_MDCFG1_tRAS_MASK ((0x1f << MMDC_MDCFG1_tRAS))
841 #define MMDC_MDCFG1_tRPA_MASK ((0x1 << MMDC_MDCFG1_tRPA))
842 #define MMDC_MDCFG1_tWR_MASK ((0x7 << MMDC_MDCFG1_tWR))
843 #define MMDC_MDCFG1_tMRD_MASK ((0xf << MMDC_MDCFG1_tMRD))
844 #define MMDC_MDCFG1_tCWL_MASK ((0x7 << MMDC_MDCFG1_tCWL))
847 #define MMDC_MDCFG2_tDLLK_MASK ((0x1ff << MMDC_MDCFG2_tDLLK))
848 #define MMDC_MDCFG2_tRTP_MASK ((0x7 << MMDC_MDCFG2_tRTP))
849 #define MMDC_MDCFG2_tWTR_MASK ((0x7 << MMDC_MDCFG2_tWTR))
850 #define MMDC_MDCFG2_tRRD_MASK ((0x7 << MMDC_MDCFG2_tRRD))
853 #define MMDC_MDRWD_tDAI_MASK ((0x1fff << MMDC_MDRWD_tDAI))
854 #define MMDC_MDRWD_RTW_SAME_MASK ((0x7 << MMDC_MDRWD_RTW_SAME))
855 #define MMDC_MDRWD_WTR_DIFF_MASK ((0x7 << MMDC_MDRWD_WTR_DIFF))
856 #define MMDC_MDRWD_WTW_DIFF_MASK ((0x7 << MMDC_MDRWD_WTW_DIFF))
857 #define MMDC_MDRWD_RTW_DIFF_MASK ((0x7 << MMDC_MDRWD_RTW_DIFF))
858 #define MMDC_MDRWD_RTR_DIFF_MASK ((0x7 << MMDC_MDRWD_RTR_DIFF))
861 #define MMDC_MDPDC_PRCT_1_MASK ((0x7 << MMDC_MDPDC_PRCT_1))
862 #define MMDC_MDPDC_PRCT_0_MASK ((0x7 << MMDC_MDPDC_PRCT_0))
863 #define MMDC_MDPDC_tCKE_MASK ((0x7 << MMDC_MDPDC_tCKE))
864 #define MMDC_MDPDC_PWDT_1_MASK ((0xf << MMDC_MDPDC_PWDT_1))
865 #define MMDC_MDPDC_PWDT_0_MASK ((0xf << MMDC_MDPDC_PWDT_0))
866 #define MMDC_MDPDC_SLOW_PD_MASK ((0x1 << MMDC_MDPDC_SLOW_PD))
867 #define MMDC_MDPDC_BOTH_CS_PD_MASK ((0x1 << MMDC_MDPDC_BOTH_CS_PD))
868 #define MMDC_MDPDC_tCKSRX_MASK ((0x7 << MMDC_MDPDC_tCKSRX))
869 #define MMDC_MDPDC_tCKSRE_MASK ((0x7 << MMDC_MDPDC_tCKSRE))
872 #define MMDC_MDASP_CS0_END_MASK ((0x7f << MMDC_MDASP_CS0_END))
875 #define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR1))
876 #define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR0))
879 #define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR3))
880 #define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR2))
883 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3))
884 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2))
885 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1))
886 #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0))
889 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3))
890 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2))
891 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1))
892 #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0))
895 #define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DM0_DEL))
896 #define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ7_DEL))
897 #define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ6_DEL))
898 #define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ5_DEL))
899 #define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ4_DEL))
900 #define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ3_DEL))
901 #define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ2_DEL))
902 #define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ1_DEL))
903 #define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ0_DEL))
906 #define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DM1_DEL))
907 #define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ15_DEL))
908 #define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ14_DEL))
909 #define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ13_DEL))
910 #define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ12_DEL))
911 #define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ11_DEL))
912 #define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ10_DEL))
913 #define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ9_DEL))
914 #define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ8_DEL))
917 #define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DM2_DEL))
918 #define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ23_DEL))
919 #define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ22_DEL))
920 #define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ21_DEL))
921 #define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ20_DEL))
922 #define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ19_DEL))
923 #define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ18_DEL))
924 #define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ17_DEL))
925 #define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ16_DEL))
928 #define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DM3_DEL))
929 #define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ31_DEL))
930 #define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ30_DEL))
931 #define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ29_DEL))
932 #define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ28_DEL))
933 #define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ27_DEL))
934 #define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ26_DEL))
935 #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL))
936 #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL))
975 u32 rsvd7[0xa8];
979 u32 fuse_regs[0x20];
980 } bank[0];
1045 u32 usbphy_pwd; /* 0x000 */
1046 u32 usbphy_pwd_set; /* 0x004 */
1047 u32 usbphy_pwd_clr; /* 0x008 */
1048 u32 usbphy_pwd_tog; /* 0x00c */
1049 u32 usbphy_tx; /* 0x010 */
1050 u32 usbphy_tx_set; /* 0x014 */
1051 u32 usbphy_tx_clr; /* 0x018 */
1052 u32 usbphy_tx_tog; /* 0x01c */
1053 u32 usbphy_rx; /* 0x020 */
1054 u32 usbphy_rx_set; /* 0x024 */
1055 u32 usbphy_rx_clr; /* 0x028 */
1056 u32 usbphy_rx_tog; /* 0x02c */
1057 u32 usbphy_ctrl; /* 0x030 */
1058 u32 usbphy_ctrl_set; /* 0x034 */
1059 u32 usbphy_ctrl_clr; /* 0x038 */
1060 u32 usbphy_ctrl_tog; /* 0x03c */
1061 u32 usbphy_status; /* 0x040 */
1063 u32 usbphy_debug0; /* 0x050 */
1064 u32 usbphy_debug0_set; /* 0x054 */
1065 u32 usbphy_debug0_clr; /* 0x058 */
1066 u32 usbphy_debug0_tog; /* 0x05c */
1068 u32 usbphy_debug1; /* 0x070 */
1069 u32 usbphy_debug1_set; /* 0x074 */
1070 u32 usbphy_debug1_clr; /* 0x078 */
1071 u32 usbphy_debug1_tog; /* 0x07c */
1072 u32 usbphy_version; /* 0x080 */
1074 u32 usb1_pll_480_ctrl; /* 0x0a0 */
1075 u32 usb1_pll_480_ctrl_set; /* 0x0a4 */
1076 u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */
1077 u32 usb1_pll_480_ctrl_tog; /* 0x0ac */
1079 u32 usb1_vbus_detect; /* 0xc0 */
1080 u32 usb1_vbus_detect_set; /* 0xc4 */
1081 u32 usb1_vbus_detect_clr; /* 0xc8 */
1082 u32 usb1_vbus_detect_tog; /* 0xcc */
1083 u32 usb1_vbus_det_stat; /* 0xd0 */
1085 u32 usb1_chrg_detect; /* 0xe0 */
1086 u32 usb1_chrg_detect_set; /* 0xe4 */
1087 u32 usb1_chrg_detect_clr; /* 0xe8 */
1088 u32 usb1_chrg_detect_tog; /* 0xec */
1089 u32 usb1_chrg_det_stat; /* 0xf0 */
1091 u32 usbphy_anactrl; /* 0x100 */
1092 u32 usbphy_anactrl_set; /* 0x104 */
1093 u32 usbphy_anactrl_clr; /* 0x108 */
1094 u32 usbphy_anactrl_tog; /* 0x10c */
1095 u32 usb1_loopback; /* 0x110 */
1096 u32 usb1_loopback_set; /* 0x114 */
1097 u32 usb1_loopback_clr; /* 0x118 */
1098 u32 usb1_loopback_tog; /* 0x11c */
1099 u32 usb1_loopback_hsfscnt; /* 0x120 */
1100 u32 usb1_loopback_hsfscnt_set; /* 0x124 */
1101 u32 usb1_loopback_hsfscnt_clr; /* 0x128 */
1102 u32 usb1_loopback_hsfscnt_tog; /* 0x12c */
1103 u32 usphy_trim_override_en; /* 0x130 */
1104 u32 usphy_trim_override_en_set; /* 0x134 */
1105 u32 usphy_trim_override_en_clr; /* 0x138 */
1106 u32 usphy_trim_override_en_tog; /* 0x13c */
1107 u32 usb1_pfda_ctrl1; /* 0x140 */
1108 u32 usb1_pfda_ctrl1_set; /* 0x144 */
1109 u32 usb1_pfda_ctrl1_clr; /* 0x148 */
1110 u32 usb1_pfda_ctrl1_tog; /* 0x14c */
1115 #define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140)