Lines Matching +full:0 +full:x0000c000
9 #define CCM_CCOSR 0x020c4060
10 #define CCM_CCGR0 0x020C4068
11 #define CCM_CCGR1 0x020C406c
12 #define CCM_CCGR2 0x020C4070
13 #define CCM_CCGR3 0x020C4074
14 #define CCM_CCGR4 0x020C4078
15 #define CCM_CCGR5 0x020C407c
16 #define CCM_CCGR6 0x020C4080
18 #define PMU_MISC2 0x020C8170
22 u32 ccr; /* 0x0000 */
26 u32 cacrr; /* 0x0010*/
30 u32 cscmr2; /* 0x0020 */
34 u32 cdcdr; /* 0x0030 */
38 u32 cscdr4; /* 0x0040 */
42 u32 ctor; /* 0x0050 */
46 u32 ccosr; /* 0x0060 */
50 u32 CCGR2; /* 0x0070 */
54 u32 CCGR6; /* 0x0080 */
57 u32 resv[0xfdd];
58 u32 analog_pll_sys; /* 0x4000 */
62 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
67 u32 analog_pll_528; /* 0x4030 */
71 u32 analog_pll_528_ss; /* 0x4040 */
73 u32 analog_pll_528_num; /* 0x4050 */
75 u32 analog_pll_528_denom; /* 0x4060 */
77 u32 analog_pll_audio; /* 0x4070 */
81 u32 analog_pll_audio_num; /* 0x4080*/
83 u32 analog_pll_audio_denom; /* 0x4090 */
85 u32 analog_pll_video; /* 0x40a0 */
89 u32 analog_pll_video_num; /* 0x40b0 */
91 u32 analog_pll_video_denom; /* 0x40c0 */
93 u32 analog_pll_enet; /* 0x40e0 */
97 u32 analog_pfd_480; /* 0x40f0 */
101 u32 analog_pfd_528; /* 0x4100 */
201 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
204 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7
208 #define MXC_CCM_CCR_OSCNT_MASK 0x7F
210 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
212 #define MXC_CCM_CCR_OSCNT_OFFSET 0
222 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
235 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
238 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
239 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
242 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
247 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
249 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
251 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
253 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
257 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
259 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
260 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
263 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
265 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
268 #define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23)
270 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
272 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
275 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
278 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
280 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
283 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
289 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
291 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
297 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
300 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
302 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
304 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
307 #define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20)
310 #define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK (0x7 << 20)
313 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
322 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
324 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
326 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
329 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
335 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
339 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21)
342 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
347 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
350 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
355 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
359 #define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22)
361 #define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19)
364 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
366 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
368 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
370 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
374 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
376 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
378 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
379 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
385 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << 22)
387 #define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F << 16)
389 #define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << 6)
391 #define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK 0x3F
392 #define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET 0
394 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
396 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
398 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
400 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
402 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
404 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
405 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
409 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
411 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
412 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18)
414 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18)
415 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
417 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
419 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
421 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
422 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
424 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
426 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15)
428 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15)
429 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16)
431 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16)
446 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
448 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
450 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
452 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
453 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
457 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
461 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
463 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22)
465 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
467 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
469 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
471 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
476 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
478 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
480 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9)
482 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6)
484 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3)
486 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
487 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
489 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
491 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
493 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
495 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
497 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
499 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
500 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
503 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15)
505 #define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12)
507 #define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0x7 << 9)
515 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
518 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
520 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15)
522 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12)
524 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9)
527 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6)
529 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3)
531 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0)
532 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0
535 #define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK (0x7 << 6)
537 #define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK (0x7 << 3)
541 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
543 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
545 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
548 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
550 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
552 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
553 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
556 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
558 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
560 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
562 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
566 #define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_MASK (0x7 << 16)
568 #define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK (0x3 << 14)
598 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
605 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
609 #define MXC_CCM_CLPCR_LPM_MASK 0x3
610 #define MXC_CCM_CLPCR_LPM_OFFSET 0
640 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
643 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
644 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
645 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
646 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
648 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
649 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
666 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
702 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
742 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
784 #define MXC_CCM_CCGR2_ESAI_CLK_OFFSET 0
806 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
875 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
903 #define MXC_CCM_CCGR5_ROM_OFFSET 0
935 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
982 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
984 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
987 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
988 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
989 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
990 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
992 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
995 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
996 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
997 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
998 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
999 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
1000 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
1001 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
1002 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
1003 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
1004 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
1005 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
1006 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0
1007 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
1009 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
1011 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
1013 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
1016 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
1018 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
1021 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
1022 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
1023 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
1024 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
1025 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
1026 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
1027 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
1028 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
1029 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
1030 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
1031 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
1032 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
1033 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
1035 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
1038 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
1039 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
1041 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
1043 #define BM_ANADIG_PLL_528_LOCK 0x80000000
1045 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
1048 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
1049 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
1050 #define BM_ANADIG_PLL_528_BYPASS 0x00010000
1052 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
1055 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
1056 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
1057 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
1058 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
1059 #define BM_ANADIG_PLL_528_ENABLE 0x00002000
1060 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
1061 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
1062 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
1063 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200
1064 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
1065 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080
1067 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E
1070 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
1073 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
1076 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
1077 #define BP_ANADIG_PLL_528_SS_STEP 0
1078 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
1080 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
1083 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
1086 #define BP_ANADIG_PLL_528_NUM_A 0
1087 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
1089 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
1092 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
1095 #define BP_ANADIG_PLL_528_DENOM_B 0
1096 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
1098 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
1100 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
1102 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
1105 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
1107 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
1110 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
1111 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
1112 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
1114 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
1117 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
1118 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
1119 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
1120 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
1121 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
1122 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
1123 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
1124 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
1125 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
1126 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
1127 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
1128 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
1129 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
1131 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
1134 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
1137 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
1138 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
1140 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
1143 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
1146 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
1147 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
1149 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
1151 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
1153 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
1156 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
1158 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
1161 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
1162 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
1163 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
1165 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
1168 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
1169 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
1170 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
1171 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
1172 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
1173 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
1174 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
1175 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
1176 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
1177 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
1178 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
1179 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
1180 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
1182 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
1185 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
1188 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
1189 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
1191 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
1194 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
1197 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
1198 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
1200 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
1202 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000
1204 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
1207 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
1208 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
1209 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
1210 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
1211 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
1212 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
1214 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
1217 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
1218 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
1219 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
1220 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
1221 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
1222 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
1223 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
1224 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
1225 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
1226 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
1227 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
1229 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
1232 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
1233 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
1235 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
1238 #define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
1239 #define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
1243 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
1244 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
1246 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
1249 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
1250 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
1252 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
1255 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
1256 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
1258 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
1261 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
1262 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
1263 #define BP_ANADIG_PFD_480_PFD0_FRAC 0
1264 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
1266 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
1268 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
1269 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
1271 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
1274 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
1275 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
1277 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
1280 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
1281 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
1283 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
1286 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
1287 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
1288 #define BP_ANADIG_PFD_528_PFD0_FRAC 0
1289 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
1291 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
1293 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
1294 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60