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120 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22
121 #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
122 #define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22)
123 #define MXC_CCM_CBCDR_EMI_PODF_RD(r) (((r) >> 22) & 0x7)
171 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22
172 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
173 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v) (((v) & 0x3) << 22)
174 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r) (((r) >> 22) & 0x3)
275 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22
276 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
277 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22)
278 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7)
346 #define MXC_CCM_CCGR0_ROM_OFFSET 22
347 #define MXC_CCM_CCGR0_ROM(v) (((v) & 0x3) << 22)
380 #define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22
381 #define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22)
385 #define MXC_CCM_CCGR1_I2C3_OFFSET 22
386 #define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22)
419 #define MXC_CCM_CCGR2_OWIRE_OFFSET 22
420 #define MXC_CCM_CCGR2_OWIRE(v) (((v) & 0x3) << 22)
452 #define MXC_CCM_CCGR3_SSI2_SSI_OFFSET 22
453 #define MXC_CCM_CCGR3_SSI2_SSI(v) (((v) & 0x3) << 22)
490 #define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET 22
491 #define MXC_CCM_CCGR4_ECSPI2_IPG(v) (((v) & 0x3) << 22)
528 #define MXC_CCM_CCGR5_EMI_WRCK_OFFSET 22
529 #define MXC_CCM_CCGR5_EMI_WRCK(v) (((v) & 0x3) << 22)
571 #define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET 22
572 #define MXC_CCM_CCGR6_CAN1_SERIAL(v) (((v) & 0x3) << 22)