Lines Matching +full:0 +full:xff
70 u32 res[0x1f1];
72 u32 fuse_regs[0x20];
73 u32 fuse_rsvd[0xe0];
100 #define IOMUX_PADNUM_MASK 0x1ff
107 PAD_CTL_NOLOOPBACK = 0x0 << 9,
108 PAD_CTL_LOOPBACK = 0x1 << 9,
109 PAD_CTL_PKE_NONE = 0x0 << 8,
110 PAD_CTL_PKE_ENABLE = 0x1 << 8,
111 PAD_CTL_PUE_KEEPER = 0x0 << 7,
112 PAD_CTL_PUE_PUD = 0x1 << 7,
113 PAD_CTL_100K_PD = 0x0 << 5,
114 PAD_CTL_100K_PU = 0x1 << 5,
115 PAD_CTL_47K_PU = 0x2 << 5,
116 PAD_CTL_22K_PU = 0x3 << 5,
117 PAD_CTL_HYS_CMOS = 0x0 << 4,
118 PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
119 PAD_CTL_ODE_CMOS = 0x0 << 3,
120 PAD_CTL_ODE_OpenDrain = 0x1 << 3,
121 PAD_CTL_DRV_NORMAL = 0x0 << 1,
122 PAD_CTL_DRV_HIGH = 0x1 << 1,
123 PAD_CTL_DRV_MAX = 0x2 << 1,
124 PAD_CTL_SRE_SLOW = 0x0 << 0,
125 PAD_CTL_SRE_FAST = 0x1 << 0
135 MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0),
136 MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1),
137 MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2),
138 MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3),
139 MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4),
140 MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5),
141 MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6),
154 MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
155 MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
156 MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
157 MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
158 MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
159 MX31_PIN_READ = IOMUX_PIN(0xff, 24),
160 MX31_PIN_WRITE = IOMUX_PIN(0xff, 25),
161 MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26),
168 MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
169 MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
170 MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
171 MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36),
172 MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
173 MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
174 MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
175 MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
176 MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
177 MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
178 MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
179 MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
180 MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
181 MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
182 MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
183 MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
184 MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
185 MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
186 MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
187 MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
188 MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
189 MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
190 MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55),
191 MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56),
192 MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57),
193 MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58),
194 MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59),
195 MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60),
196 MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61),
197 MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62),
198 MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63),
199 MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64),
200 MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65),
201 MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66),
202 MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67),
203 MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68),
204 MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69),
205 MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70),
206 MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71),
207 MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72),
211 MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76),
212 MX31_PIN_DE_B = IOMUX_PIN(0xff, 77),
213 MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78),
214 MX31_PIN_TDO = IOMUX_PIN(0xff, 79),
215 MX31_PIN_TDI = IOMUX_PIN(0xff, 80),
216 MX31_PIN_TMS = IOMUX_PIN(0xff, 81),
217 MX31_PIN_TCK = IOMUX_PIN(0xff, 82),
218 MX31_PIN_RTCK = IOMUX_PIN(0xff, 83),
223 MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88),
224 MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89),
225 MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90),
226 MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91),
231 MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96),
232 MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97),
233 MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98),
234 MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99),
236 MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101),
237 MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102),
253 MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118),
254 MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119),
255 MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120),
256 MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121),
257 MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122),
258 MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123),
259 MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124),
260 MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125),
261 MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126),
262 MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127),
263 MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128),
264 MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129),
265 MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130),
266 MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131),
271 MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136),
272 MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137),
275 MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140),
276 MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141),
279 MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144),
280 MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145),
283 MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148),
284 MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149),
301 MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166),
302 MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167),
303 MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168),
304 MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169),
305 MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170),
306 MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171),
307 MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172),
308 MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173),
309 MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174),
310 MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175),
311 MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176),
312 MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177),
313 MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178),
314 MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179),
315 MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180),
316 MX31_PIN_D0 = IOMUX_PIN(0xff, 181),
317 MX31_PIN_D1 = IOMUX_PIN(0xff, 182),
318 MX31_PIN_D2 = IOMUX_PIN(0xff, 183),
319 MX31_PIN_D3 = IOMUX_PIN(0xff, 184),
320 MX31_PIN_D4 = IOMUX_PIN(0xff, 185),
321 MX31_PIN_D5 = IOMUX_PIN(0xff, 186),
322 MX31_PIN_D6 = IOMUX_PIN(0xff, 187),
323 MX31_PIN_D7 = IOMUX_PIN(0xff, 188),
324 MX31_PIN_D8 = IOMUX_PIN(0xff, 189),
325 MX31_PIN_D9 = IOMUX_PIN(0xff, 190),
326 MX31_PIN_D10 = IOMUX_PIN(0xff, 191),
327 MX31_PIN_D11 = IOMUX_PIN(0xff, 192),
328 MX31_PIN_D12 = IOMUX_PIN(0xff, 193),
329 MX31_PIN_D13 = IOMUX_PIN(0xff, 194),
330 MX31_PIN_D14 = IOMUX_PIN(0xff, 195),
331 MX31_PIN_D15 = IOMUX_PIN(0xff, 196),
339 MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204),
340 MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205),
341 MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206),
342 MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207),
343 MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208),
344 MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209),
345 MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210),
346 MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211),
347 MX31_PIN_SDWE = IOMUX_PIN(0xff, 212),
348 MX31_PIN_CAS = IOMUX_PIN(0xff, 213),
349 MX31_PIN_RAS = IOMUX_PIN(0xff, 214),
350 MX31_PIN_RW = IOMUX_PIN(0xff, 215),
351 MX31_PIN_BCLK = IOMUX_PIN(0xff, 216),
352 MX31_PIN_LBA = IOMUX_PIN(0xff, 217),
353 MX31_PIN_ECB = IOMUX_PIN(0xff, 218),
354 MX31_PIN_CS5 = IOMUX_PIN(0xff, 219),
355 MX31_PIN_CS4 = IOMUX_PIN(0xff, 220),
356 MX31_PIN_CS3 = IOMUX_PIN(0xff, 221),
357 MX31_PIN_CS2 = IOMUX_PIN(0xff, 222),
358 MX31_PIN_CS1 = IOMUX_PIN(0xff, 223),
359 MX31_PIN_CS0 = IOMUX_PIN(0xff, 224),
360 MX31_PIN_OE = IOMUX_PIN(0xff, 225),
361 MX31_PIN_EB1 = IOMUX_PIN(0xff, 226),
362 MX31_PIN_EB0 = IOMUX_PIN(0xff, 227),
363 MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228),
364 MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229),
365 MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230),
366 MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231),
367 MX31_PIN_SD31 = IOMUX_PIN(0xff, 232),
368 MX31_PIN_SD30 = IOMUX_PIN(0xff, 233),
369 MX31_PIN_SD29 = IOMUX_PIN(0xff, 234),
370 MX31_PIN_SD28 = IOMUX_PIN(0xff, 235),
371 MX31_PIN_SD27 = IOMUX_PIN(0xff, 236),
372 MX31_PIN_SD26 = IOMUX_PIN(0xff, 237),
373 MX31_PIN_SD25 = IOMUX_PIN(0xff, 238),
374 MX31_PIN_SD24 = IOMUX_PIN(0xff, 239),
375 MX31_PIN_SD23 = IOMUX_PIN(0xff, 240),
376 MX31_PIN_SD22 = IOMUX_PIN(0xff, 241),
377 MX31_PIN_SD21 = IOMUX_PIN(0xff, 242),
378 MX31_PIN_SD20 = IOMUX_PIN(0xff, 243),
379 MX31_PIN_SD19 = IOMUX_PIN(0xff, 244),
380 MX31_PIN_SD18 = IOMUX_PIN(0xff, 245),
381 MX31_PIN_SD17 = IOMUX_PIN(0xff, 246),
382 MX31_PIN_SD16 = IOMUX_PIN(0xff, 247),
383 MX31_PIN_SD15 = IOMUX_PIN(0xff, 248),
384 MX31_PIN_SD14 = IOMUX_PIN(0xff, 249),
385 MX31_PIN_SD13 = IOMUX_PIN(0xff, 250),
386 MX31_PIN_SD12 = IOMUX_PIN(0xff, 251),
387 MX31_PIN_SD11 = IOMUX_PIN(0xff, 252),
388 MX31_PIN_SD10 = IOMUX_PIN(0xff, 253),
389 MX31_PIN_SD9 = IOMUX_PIN(0xff, 254),
390 MX31_PIN_SD8 = IOMUX_PIN(0xff, 255),
391 MX31_PIN_SD7 = IOMUX_PIN(0xff, 256),
392 MX31_PIN_SD6 = IOMUX_PIN(0xff, 257),
393 MX31_PIN_SD5 = IOMUX_PIN(0xff, 258),
394 MX31_PIN_SD4 = IOMUX_PIN(0xff, 259),
395 MX31_PIN_SD3 = IOMUX_PIN(0xff, 260),
396 MX31_PIN_SD2 = IOMUX_PIN(0xff, 261),
397 MX31_PIN_SD1 = IOMUX_PIN(0xff, 262),
398 MX31_PIN_SD0 = IOMUX_PIN(0xff, 263),
399 MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264),
400 MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265),
401 MX31_PIN_A25 = IOMUX_PIN(0xff, 266),
402 MX31_PIN_A24 = IOMUX_PIN(0xff, 267),
403 MX31_PIN_A23 = IOMUX_PIN(0xff, 268),
404 MX31_PIN_A22 = IOMUX_PIN(0xff, 269),
405 MX31_PIN_A21 = IOMUX_PIN(0xff, 270),
406 MX31_PIN_A20 = IOMUX_PIN(0xff, 271),
407 MX31_PIN_A19 = IOMUX_PIN(0xff, 272),
408 MX31_PIN_A18 = IOMUX_PIN(0xff, 273),
409 MX31_PIN_A17 = IOMUX_PIN(0xff, 274),
410 MX31_PIN_A16 = IOMUX_PIN(0xff, 275),
411 MX31_PIN_A14 = IOMUX_PIN(0xff, 276),
412 MX31_PIN_A15 = IOMUX_PIN(0xff, 277),
413 MX31_PIN_A13 = IOMUX_PIN(0xff, 278),
414 MX31_PIN_A12 = IOMUX_PIN(0xff, 279),
415 MX31_PIN_A11 = IOMUX_PIN(0xff, 280),
416 MX31_PIN_MA10 = IOMUX_PIN(0xff, 281),
417 MX31_PIN_A10 = IOMUX_PIN(0xff, 282),
418 MX31_PIN_A9 = IOMUX_PIN(0xff, 283),
419 MX31_PIN_A8 = IOMUX_PIN(0xff, 284),
420 MX31_PIN_A7 = IOMUX_PIN(0xff, 285),
421 MX31_PIN_A6 = IOMUX_PIN(0xff, 286),
422 MX31_PIN_A5 = IOMUX_PIN(0xff, 287),
423 MX31_PIN_A4 = IOMUX_PIN(0xff, 288),
424 MX31_PIN_A3 = IOMUX_PIN(0xff, 289),
425 MX31_PIN_A2 = IOMUX_PIN(0xff, 290),
426 MX31_PIN_A1 = IOMUX_PIN(0xff, 291),
427 MX31_PIN_A0 = IOMUX_PIN(0xff, 292),
428 MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293),
429 MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294),
430 MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295),
431 MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296),
432 MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297),
433 MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298),
434 MX31_PIN_CKIL = IOMUX_PIN(0xff, 299),
435 MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300),
436 MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301),
437 MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302),
438 MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303),
439 MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304),
440 MX31_PIN_CLKO = IOMUX_PIN(0xff, 305),
441 MX31_PIN_POR_B = IOMUX_PIN(0xff, 306),
442 MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307),
443 MX31_PIN_CKIH = IOMUX_PIN(0xff, 308),
458 MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323),
460 MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325),
469 MUX_PGP_FIRI = 1 << 0,
538 #define CCM_BASE 0x53f80000
539 #define CCM_CCMR (CCM_BASE + 0x00)
540 #define CCM_PDR0 (CCM_BASE + 0x04)
541 #define CCM_PDR1 (CCM_BASE + 0x08)
542 #define CCM_RCSR (CCM_BASE + 0x0c)
543 #define CCM_MPCTL (CCM_BASE + 0x10)
544 #define CCM_UPCTL (CCM_BASE + 0x14)
545 #define CCM_SPCTL (CCM_BASE + 0x18)
546 #define CCM_COSR (CCM_BASE + 0x1C)
547 #define CCM_CGR0 (CCM_BASE + 0x20)
548 #define CCM_CGR1 (CCM_BASE + 0x24)
549 #define CCM_CGR2 (CCM_BASE + 0x28)
558 #define MX31_IIM_BASE_ADDR 0x5001C000
561 #define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26)
562 #define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23)
563 #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
564 #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
565 #define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
566 #define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
567 #define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
568 #define PDR0_MCU_PODF(x) ((x) & 0x7)
570 #define PDR1_USB_PRDF(x) (((x) & 0x3) << 30)
571 #define PDR1_USB_PODF(x) (((x) & 0x7) << 27)
572 #define PDR1_FIRI_PRDF(x) (((x) & 0x7) << 24)
573 #define PDR1_FIRI_PODF(x) (((x) & 0x3f) << 18)
574 #define PDR1_SSI2_PRDF(x) (((x) & 0x7) << 15)
575 #define PDR1_SSI2_PODF(x) (((x) & 0x3f) << 9)
576 #define PDR1_SSI1_PRDF(x) (((x) & 0x7) << 6)
577 #define PDR1_SSI1_PODF(x) ((x) & 0x3f)
579 #define PLL_BRMO(x) (((x) & 0x1) << 31)
580 #define PLL_PD(x) (((x) & 0xf) << 26)
581 #define PLL_MFD(x) (((x) & 0x3ff) << 16)
582 #define PLL_MFI(x) (((x) & 0xf) << 10)
583 #define PLL_MFN(x) (((x) & 0x3ff) << 0)
585 #define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f)
586 #define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7)
587 #define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f)
588 #define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7)
589 #define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7)
590 #define GET_PDR0_IPG_PODF(x) (((x) >> 6) & 0x3)
591 #define GET_PDR0_MAX_PODF(x) (((x) >> 3) & 0x7)
592 #define GET_PDR0_MCU_PODF(x) ((x) & 0x7)
594 #define GET_PLL_PD(x) (((x) >> 26) & 0xf)
595 #define GET_PLL_MFD(x) (((x) >> 16) & 0x3ff)
596 #define GET_PLL_MFI(x) (((x) >> 10) & 0xf)
597 #define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff)
600 #define WEIM_ESDCTL0 0xB8001000
601 #define WEIM_ESDCFG0 0xB8001004
602 #define WEIM_ESDCTL1 0xB8001008
603 #define WEIM_ESDCFG1 0xB800100C
604 #define WEIM_ESDMISC 0xB8001010
606 #define UART1_BASE 0x43F90000
607 #define UART2_BASE 0x43F94000
608 #define UART3_BASE 0x5000C000
609 #define UART4_BASE 0x43FB0000
610 #define UART5_BASE 0x43FB4000
612 #define I2C1_BASE_ADDR 0x43f80000
614 #define I2C2_BASE_ADDR 0x43F98000
616 #define I2C3_BASE_ADDR 0x43f84000
620 #define ESDCTL_CMD_RW (0 << 28)
634 #define ESDCTL_PRCT(x) ((x) << 0)
636 #define ESDCTL_BASE_ADDR 0xB8001000
643 (wws) << 4 | (edc) << 0)
649 (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
656 (age) << 2 | (cnc2) << 1 | (fce) << 0)
658 #define WEIM_BASE 0xb8002000
660 #define IOMUXC_BASE 0x43FAC000
661 #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
662 #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
664 #define IPU_BASE 0x53fc0000
675 #define IPU_CONF_CSI_EN (1<<0)
677 #define ARM_PPMRR 0x40000015
679 #define WDOG1_BASE_ADDR 0x53FDC000
684 #define GPIO1_BASE_ADDR 0x53FCC000
685 #define GPIO2_BASE_ADDR 0x53FD0000
686 #define GPIO3_BASE_ADDR 0x53FA4000
687 #define GPIO_DR 0x00000000 /* data register */
688 #define GPIO_GDIR 0x00000004 /* direction register */
689 #define GPIO_PSR 0x00000008 /* pad status register */
696 #define MUX_CTL_OUT_GPIO_DR (0 << 4)
704 #define MUX_CTL_IN_NONE (0 << 0)
705 #define MUX_CTL_IN_GPIO (1 << 0)
706 #define MUX_CTL_IN_FUNC (2 << 0)
707 #define MUX_CTL_IN_ALT1 (4 << 0)
708 #define MUX_CTL_IN_ALT2 (8 << 0)
716 /* 0x00 .. 0x7b */
717 #define MUX_CTL_CSPI3_MISO 0x0c
718 #define MUX_CTL_CSPI3_SCLK 0x0d
719 #define MUX_CTL_CSPI3_SPI_RDY 0x0e
720 #define MUX_CTL_CSPI3_MOSI 0x13
722 #define MUX_CTL_SD1_DATA1 0x18
723 #define MUX_CTL_SD1_DATA2 0x19
724 #define MUX_CTL_SD1_DATA3 0x1a
725 #define MUX_CTL_SD1_CMD 0x1d
726 #define MUX_CTL_SD1_CLK 0x1e
727 #define MUX_CTL_SD1_DATA0 0x1f
729 #define MUX_CTL_USBH2_DATA1 0x40
730 #define MUX_CTL_USBH2_DIR 0x44
731 #define MUX_CTL_USBH2_STP 0x45
732 #define MUX_CTL_USBH2_NXT 0x46
733 #define MUX_CTL_USBH2_DATA0 0x47
734 #define MUX_CTL_USBH2_CLK 0x4B
736 #define MUX_CTL_TXD2 0x70
737 #define MUX_CTL_RTS2 0x71
738 #define MUX_CTL_CTS2 0x72
739 #define MUX_CTL_RXD2 0x77
741 #define MUX_CTL_RTS1 0x7c
742 #define MUX_CTL_CTS1 0x7d
743 #define MUX_CTL_DTR_DCE1 0x7e
744 #define MUX_CTL_DSR_DCE1 0x7f
745 #define MUX_CTL_CSPI2_SCLK 0x80
746 #define MUX_CTL_CSPI2_SPI_RDY 0x81
747 #define MUX_CTL_RXD1 0x82
748 #define MUX_CTL_TXD1 0x83
749 #define MUX_CTL_CSPI2_MISO 0x84
750 #define MUX_CTL_CSPI2_SS0 0x85
751 #define MUX_CTL_CSPI2_SS1 0x86
752 #define MUX_CTL_CSPI2_SS2 0x87
753 #define MUX_CTL_CSPI1_SS2 0x88
754 #define MUX_CTL_CSPI1_SCLK 0x89
755 #define MUX_CTL_CSPI1_SPI_RDY 0x8a
756 #define MUX_CTL_CSPI2_MOSI 0x8b
757 #define MUX_CTL_CSPI1_MOSI 0x8c
758 #define MUX_CTL_CSPI1_MISO 0x8d
759 #define MUX_CTL_CSPI1_SS0 0x8e
760 #define MUX_CTL_CSPI1_SS1 0x8f
761 #define MUX_CTL_STXD6 0x90
762 #define MUX_CTL_SRXD6 0x91
763 #define MUX_CTL_SCK6 0x92
764 #define MUX_CTL_SFS6 0x93
766 #define MUX_CTL_STXD3 0x9C
767 #define MUX_CTL_SRXD3 0x9D
768 #define MUX_CTL_SCK3 0x9E
769 #define MUX_CTL_SFS3 0x9F
771 #define MUX_CTL_NFC_WP 0xD0
772 #define MUX_CTL_NFC_CE 0xD1
773 #define MUX_CTL_NFC_RB 0xD2
774 #define MUX_CTL_NFC_WE 0xD4
775 #define MUX_CTL_NFC_RE 0xD5
776 #define MUX_CTL_NFC_ALE 0xD6
777 #define MUX_CTL_NFC_CLE 0xD7
780 #define MUX_CTL_CAPTURE 0x150
781 #define MUX_CTL_COMPARE 0x151
825 #define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
826 #define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270)
827 #define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274)
828 #define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278)
829 #define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C)
830 #define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280)
831 #define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284)
832 #define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288)
833 #define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C)
834 #define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290)
835 #define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294)
836 #define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298)
837 #define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C)
838 #define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0)
839 #define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4)
840 #define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8)
841 #define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC)
842 #define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0)
843 #define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4)
844 #define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8)
845 #define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC)
846 #define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0)
847 #define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4)
848 #define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8)
849 #define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC)
850 #define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0)
851 #define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4)
852 #define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8)
853 #define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC)
858 #define IPU_MEM_BASE 0x70000000
859 #define CSD0_BASE 0x80000000
860 #define CSD1_BASE 0x90000000
861 #define CS0_BASE 0xA0000000
862 #define CS1_BASE 0xA8000000
863 #define CS2_BASE 0xB0000000
864 #define CS3_BASE 0xB2000000
865 #define CS4_BASE 0xB4000000
866 #define CS4_PSRAM_BASE 0xB5000000
867 #define CS5_BASE 0xB6000000
868 #define PCMCIA_MEM_BASE 0xC0000000
873 #define NFC_BASE_ADDR 0xB8000000
876 #define SDHC1_BASE_ADDR 0x50004000
877 #define SDHC2_BASE_ADDR 0x50008000
882 #define IRAM_BASE_ADDR 0x1FFFC000
885 #define MX31_AIPS1_BASE_ADDR 0x43f00000
886 #define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000)
887 #define IMX_USB_PORT_OFFSET 0x200
893 #define MXC_CSPICTRL_EN (1 << 0)
901 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
902 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
903 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
906 #define MXC_CSPICTRL_MAXBITS 0x1f
913 0x43fa4000, \
914 0x50010000, \
915 0x53f84000,