Lines Matching refs:u32
13 u32 ctrl; /* Controls operation of the EMC */
14 u32 status; /* Provides EMC status information */
15 u32 config; /* Configures operation of the EMC */
16 u32 reserved0[5];
17 u32 control; /* Controls dyn memory operation */
18 u32 refresh; /* Configures dyn memory refresh operation */
19 u32 read_config; /* Configures the dyn memory read strategy */
20 u32 reserved1;
21 u32 t_rp; /* Precharge command period */
22 u32 t_ras; /* Active to precharge command period */
23 u32 t_srex; /* Self-refresh exit time */
24 u32 reserved2[2];
25 u32 t_wr; /* Write recovery time */
26 u32 t_rc; /* Active to active command period */
27 u32 t_rfc; /* Auto-refresh period */
28 u32 t_xsr; /* Exit self-refresh to active command time */
29 u32 t_rrd; /* Active bank A to active bank B latency */
30 u32 t_mrd; /* Load mode register to active command time */
31 u32 t_cdlr; /* Last data in to read command time */
32 u32 reserved3[8];
33 u32 extended_wait; /* time for static memory rd/wr transfers */
34 u32 reserved4[31];
35 u32 config0; /* Configuration information for the SDRAM */
36 u32 rascas0; /* RAS and CAS latencies for the SDRAM */
37 u32 reserved5[6];
38 u32 config1; /* Configuration information for the SDRAM */
39 u32 rascas1; /* RAS and CAS latencies for the SDRAM */
40 u32 reserved6[54];
42 u32 config; /* Static memory configuration */
43 u32 waitwen; /* Delay from chip select to write enable */
44 u32 waitoen; /* Delay to output enable */
45 u32 waitrd; /* Delay to a read access */
46 u32 waitpage; /* Delay for async page mode read */
47 u32 waitwr; /* Delay to a write access */
48 u32 waitturn; /* Number of bus turnaround cycles */
49 u32 reserved;
51 u32 reserved7[96];
53 u32 control; /* Control register for AHB */
54 u32 status; /* Status register for AHB */
55 u32 timeout; /* Timeout register for AHB */
56 u32 reserved[5];
80 u32 cmddelay;
81 u32 config0;
82 u32 rascas0;
83 u32 rdconfig;
84 u32 trp;
85 u32 tras;
86 u32 tsrex;
87 u32 twr;
88 u32 trc;
89 u32 trfc;
90 u32 txsr;
91 u32 trrd;
92 u32 tmrd;
93 u32 tcdlr;
94 u32 refresh;
95 u32 mode;
96 u32 emode;