Lines Matching +full:emc +full:- +full:mode +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0+ */
11 /* EMC Registers */
13 u32 ctrl; /* Controls operation of the EMC */
14 u32 status; /* Provides EMC status information */
15 u32 config; /* Configures operation of the EMC */
23 u32 t_srex; /* Self-refresh exit time */
27 u32 t_rfc; /* Auto-refresh period */
28 u32 t_xsr; /* Exit self-refresh to active command time */
30 u32 t_mrd; /* Load mode register to active command time */
46 u32 waitpage; /* Delay for async page mode read */
61 #define EMC_STAT_CONFIG_WP (1 << 20)
62 #define EMC_STAT_CONFIG_EW (1 << 8)
63 #define EMC_STAT_CONFIG_PB (1 << 7)
64 #define EMC_STAT_CONFIG_PC (1 << 6)
65 #define EMC_STAT_CONFIG_PM (1 << 3)
67 #define EMC_STAT_CONFIG_16BIT (1 << 0)
71 #define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F)
73 #define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F)
74 #define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F)
75 #define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F)
76 #define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F)
78 /* EMC settings for DRAM */
95 u32 mode; member