Lines Matching defs:clk_pm_regs

15 struct clk_pm_regs {  struct
16 	u32 reserved0[5];
17 	u32 boot_map;		/* Boot Map Control Register		*/
18 	u32 p0_intr_er;		/* Port 0/1 Start and Interrupt Enable	*/
19 	u32 usbdiv_ctrl;	/* USB Clock Pre-Divide Register	*/
21 	u32 start_er_int;	/* Start Enable Register		*/
22 	u32 start_rsr_int;	/* Start Raw Status Register		*/
23 	u32 start_sr_int;	/* Start Status Register		*/
24 	u32 start_apr_int;	/* Start Activation Polarity Register	*/
26 	u32 start_er_pin;	/* Start Enable Register		*/
27 	u32 start_rsr_pin;	/* Start Raw Status Register		*/
28 	u32 start_sr_pin;	/* Start Status Register		*/
29 	u32 start_apr_pin;	/* Start Activation Polarity Register	*/
31 	u32 hclkdiv_ctrl;	/* HCLK Divider Control Register	*/
32 	u32 pwr_ctrl;		/* Power Control Register		*/
33 	u32 pll397_ctrl;	/* PLL397 Control Register		*/
34 	u32 osc_ctrl;		/* Main Oscillator Control Register	*/
35 	u32 sysclk_ctrl;	/* SYSCLK Control Register		*/
36 	u32 lcdclk_ctrl;	/* LCD Clock Control Register		*/
37 	u32 hclkpll_ctrl;	/* HCLK PLL Control Register		*/
38 	u32 reserved1;
39 	u32 adclk_ctrl1;	/* ADC Clock Control1 Register		*/
40 	u32 usb_ctrl;		/* USB Control Register			*/
41 	u32 sdramclk_ctrl;	/* SDRAM Clock Control Register		*/
42 	u32 ddr_lap_nom;	/* DDR Calibration Nominal Value	*/
43 	u32 ddr_lap_count;	/* DDR Calibration Measured Value	*/
44 	u32 ddr_cal_delay;	/* DDR Calibration Delay Value		*/
45 	u32 ssp_ctrl;		/* SSP Control Register			*/
46 	u32 i2s_ctrl;		/* I2S Clock Control Register		*/
47 	u32 ms_ctrl;		/* Memory Card Control Register		*/
48 	u32 reserved2[3];
49 	u32 macclk_ctrl;	/* Ethernet MAC Clock Control Register	*/
50 	u32 reserved3[4];
51 	u32 test_clk;		/* Test Clock Selection Register	*/
52 	u32 sw_int;		/* Software Interrupt Register		*/
53 	u32 i2cclk_ctrl;	/* I2C Clock Control Register		*/
54 	u32 keyclk_ctrl;	/* Keyboard Scan Clock Control Register	*/
55 	u32 adclk_ctrl;		/* ADC Clock Control Register		*/
56 	u32 pwmclk_ctrl;	/* PWM Clock Control Register		*/
57 	u32 timclk_ctrl;	/* Watchdog and Highspeed Timer Control */
58 	u32 timclk_ctrl1;	/* Motor and Timer Clock Control	*/
59 	u32 spi_ctrl;		/* SPI Control Register			*/
60 	u32 flashclk_ctrl;	/* NAND Flash Clock Control Register	*/
61 	u32 reserved4;
62 	u32 u3clk;		/* UART 3 Clock Control Register	*/
63 	u32 u4clk;		/* UART 4 Clock Control Register	*/
64 	u32 u5clk;		/* UART 5 Clock Control Register	*/
65 	u32 u6clk;		/* UART 6 Clock Control Register	*/
66 	u32 irdaclk;		/* IrDA Clock Control Register		*/
67 	u32 uartclk_ctrl;	/* UART Clock Control Register		*/
68 	u32 dmaclk_ctrl;	/* DMA Clock Control Register		*/
69 	u32 autoclk_ctrl;	/* Autoclock Control Register		*/