Lines Matching +full:0 +full:xc8
18 #define LPDDR4_MR3 0xf1
19 #define LPDDR4_PHY_DMIPinPresent 0x1
21 #define LPDDR4_MR3 0x31
22 #define LPDDR4_PHY_DMIPinPresent 0x0
26 #define LPDDR4_CS 0x1
28 #define LPDDR4_CS 0x3
32 #define LPDDR4_HDT_CTL_2D 0xC8
33 #define LPDDR4_HDT_CTL_3200_1D 0xC8
34 #define LPDDR4_HDT_CTL_400_1D 0xC8
35 #define LPDDR4_HDT_CTL_100_1D 0xC8
38 #define LPDDR4_TRAIN_SEQ_P2 0x121f
39 #define LPDDR4_TRAIN_SEQ_P1 0x121f
40 #define LPDDR4_TRAIN_SEQ_P0 0x121f
41 #define LPDDR4_TRAIN_SEQ_100 0x121f
42 #define LPDDR4_TRAIN_SEQ_400 0x121f
45 #define LPDDR4_2D_WEIGHT 0x1f7f
47 #define LPDDR4_CATRAIN_3200_1d 0
48 #define LPDDR4_CATRAIN_400 0
49 #define LPDDR4_CATRAIN_100 0
50 #define LPDDR4_CATRAIN_3200_2d 0
60 #define LPDDR4_RTT_DIS 0
69 #define LPDDR4_PHY_ADDR_RON60 0x1
70 #define LPDDR4_PHY_ADDR_RON40 0x3
71 #define LPDDR4_PHY_ADDR_RON30 0x7
72 #define LPDDR4_PHY_ADDR_RON24 0xf
73 #define LPDDR4_PHY_ADDR_RON20 0x1f
87 #define LPDDR4_VREF_VALUE_CA ((1 << 6) | (0xd))
88 #define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6) | (0xd))
89 #define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6) | (0xd))
90 #define LPDDR4_MR22_RANK0 ((0 << 5) | (1 << 4) | (0 << 3) | \