Lines Matching defs:gpc_reg
289 struct gpc_reg { struct
290 u32 lpcr_bsc;
291 u32 lpcr_ad;
292 u32 lpcr_cpu1;
293 u32 lpcr_cpu2;
294 u32 lpcr_cpu3;
295 u32 slpcr;
296 u32 mst_cpu_mapping;
297 u32 mmdc_cpu_mapping;
298 u32 mlpcr;
299 u32 pgc_ack_sel;
300 u32 pgc_ack_sel_m4;
301 u32 gpc_misc;
302 u32 imr1_core0;
303 u32 imr2_core0;
304 u32 imr3_core0;
305 u32 imr4_core0;
306 u32 imr1_core1;
307 u32 imr2_core1;
308 u32 imr3_core1;
309 u32 imr4_core1;
310 u32 imr1_cpu1;
311 u32 imr2_cpu1;
312 u32 imr3_cpu1;
313 u32 imr4_cpu1;
314 u32 imr1_cpu3;
315 u32 imr2_cpu3;
316 u32 imr3_cpu3;
317 u32 imr4_cpu3;
318 u32 isr1_cpu0;
319 u32 isr2_cpu0;
320 u32 isr3_cpu0;
321 u32 isr4_cpu0;
322 u32 isr1_cpu1;
323 u32 isr2_cpu1;
324 u32 isr3_cpu1;
325 u32 isr4_cpu1;
326 u32 isr1_cpu2;
327 u32 isr2_cpu2;
328 u32 isr3_cpu2;
329 u32 isr4_cpu2;
330 u32 isr1_cpu3;
331 u32 isr2_cpu3;
332 u32 isr3_cpu3;
333 u32 isr4_cpu3;
334 u32 slt0_cfg;
335 u32 slt1_cfg;
336 u32 slt2_cfg;
337 u32 slt3_cfg;
338 u32 slt4_cfg;
339 u32 slt5_cfg;
340 u32 slt6_cfg;
341 u32 slt7_cfg;
342 u32 slt8_cfg;
343 u32 slt9_cfg;
344 u32 slt10_cfg;
345 u32 slt11_cfg;
346 u32 slt12_cfg;
347 u32 slt13_cfg;
348 u32 slt14_cfg;
349 u32 pgc_cpu_0_1_mapping;
350 u32 cpu_pgc_up_trg;
351 u32 mix_pgc_up_trg;
352 u32 pu_pgc_up_trg;
353 u32 cpu_pgc_dn_trg;
354 u32 mix_pgc_dn_trg;
355 u32 pu_pgc_dn_trg;
356 u32 lpcr_bsc2;
357 u32 pgc_cpu_2_3_mapping;
358 u32 lps_cpu0;
359 u32 lps_cpu1;
360 u32 lps_cpu2;
361 u32 lps_cpu3;
362 u32 gpc_gpr;
363 u32 gtor;
364 u32 debug_addr1;
365 u32 debug_addr2;
366 u32 cpu_pgc_up_status1;
367 u32 mix_pgc_up_status0;
368 u32 mix_pgc_up_status1;
369 u32 mix_pgc_up_status2;
370 u32 m4_mix_pgc_up_status0;
371 u32 m4_mix_pgc_up_status1;
372 u32 m4_mix_pgc_up_status2;
373 u32 pu_pgc_up_status0;
374 u32 pu_pgc_up_status1;
375 u32 pu_pgc_up_status2;
376 u32 m4_pu_pgc_up_status0;
377 u32 m4_pu_pgc_up_status1;
378 u32 m4_pu_pgc_up_status2;
379 u32 a53_lp_io_0;
380 u32 a53_lp_io_1;
381 u32 a53_lp_io_2;
382 u32 cpu_pgc_dn_status1;
383 u32 mix_pgc_dn_status0;
384 u32 mix_pgc_dn_status1;
385 u32 mix_pgc_dn_status2;
386 u32 m4_mix_pgc_dn_status0;
387 u32 m4_mix_pgc_dn_status1;
388 u32 m4_mix_pgc_dn_status2;
389 u32 pu_pgc_dn_status0;
390 u32 pu_pgc_dn_status1;
391 u32 pu_pgc_dn_status2;
392 u32 m4_pu_pgc_dn_status0;
393 u32 m4_pu_pgc_dn_status1;
394 u32 m4_pu_pgc_dn_status2;
395 u32 res[3];
396 u32 mix_pdn_flg;
397 u32 pu_pdn_flg;
398 u32 m4_mix_pdn_flg;
399 u32 m4_pu_pdn_flg;
400 u32 imr1_core2;
401 u32 imr2_core2;
402 u32 imr3_core2;
403 u32 imr4_core2;
404 u32 imr1_core3;
405 u32 imr2_core3;
406 u32 imr3_core3;
407 u32 imr4_core3;
408 u32 pgc_ack_sel_pu;
409 u32 pgc_ack_sel_m4_pu;
410 u32 slt15_cfg;
411 u32 slt16_cfg;
412 u32 slt17_cfg;
413 u32 slt18_cfg;
414 u32 slt19_cfg;
415 u32 gpc_pu_pwrhsk;
416 u32 slt0_cfg_pu;
417 u32 slt1_cfg_pu;
418 u32 slt2_cfg_pu;
419 u32 slt3_cfg_pu;
420 u32 slt4_cfg_pu;
421 u32 slt5_cfg_pu;
422 u32 slt6_cfg_pu;
423 u32 slt7_cfg_pu;
424 u32 slt8_cfg_pu;
425 u32 slt9_cfg_pu;
426 u32 slt10_cfg_pu;
427 u32 slt11_cfg_pu;
428 u32 slt12_cfg_pu;
429 u32 slt13_cfg_pu;
430 u32 slt14_cfg_pu;
431 u32 slt15_cfg_pu;
432 u32 slt16_cfg_pu;
433 u32 slt17_cfg_pu;
434 u32 slt18_cfg_pu;
435 u32 slt19_cfg_pu;