Lines Matching refs:IMX_EIM_BASE

52 #define IMX_EIM_BASE               (0x20000 + IMX_IO_BASE)  macro
70 #define CS0U __REG(IMX_EIM_BASE)        /* Chip Select 0 Upper Register */
71 #define CS0L __REG(IMX_EIM_BASE + 0x4)  /* Chip Select 0 Lower Register */
72 #define CS1U __REG(IMX_EIM_BASE + 0x8)  /* Chip Select 1 Upper Register */
73 #define CS1L __REG(IMX_EIM_BASE + 0xc)  /* Chip Select 1 Lower Register */
74 #define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
75 #define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
76 #define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
77 #define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
78 #define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
79 #define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
80 #define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
81 #define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
82 #define EIM  __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */