Lines Matching refs:IMX_DMAC_BASE
37 #define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) macro
334 #define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
335 #define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
336 #define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
337 #define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
338 #define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
339 #define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
340 #define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
341 #define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
342 #define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
343 #define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */
344 #define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */
345 #define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */
346 #define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */
347 #define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */
348 #define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
349 #define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
350 #define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
351 #define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */
352 #define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
353 #define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
354 #define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
355 #define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */