Lines Matching +full:0 +full:x8c8

10 #define ALWAYSON_CTRL_BASE			0xF7800000
13 	u32 ctrl0;		/*0x0*/
19 	u32 stat0;		/*0x10*/
26 	u32 secondary_int_en0;	/*0x44*/
32 	u32 mcu_wkup_int_en6;	/*0x54*/
38 	u32 mcu_wkup_int_en5;	/*0x64*/
44 	u32 mcu_wkup_int_en4;	/*0x94*/
50 	u32 mcu_wkup_int_en0;	/*0xa8*/
54 	u32 mcu_wkup_int_en1;	/*0xb4*/
60 	u32 int_statr;		/*0xc4*/
64 	u32 int_en_set;		/*0xd0*/
70 	u32 int_statr1;		/*0xc4*/
74 	u32 int_en_set1;	/*0xf0*/
80 	u32 timer_en0;		/*0x1d0*/
85 	u32 timer_en4;		/*0x1f0*/
90 	u32 mcu_subsys_ctrl0;	/*0x400*/
101 	u32 mcu_subsys_stat0;	/*0x440*/
112 	u32 clk4_en;		/*0x630*/
116 	u32 clk5_en;		/*0x63c*/
122 	u32 rst4_en;		/*0x6f0*/
126 	u32 rst5_en;		/*0x6fc*/
132 	u32 pw_clk0_en;		/*0x800*/
138 	u32 pw_rst0_en;		/*0x810*/
144 	u32 pw_isoen0;		/*0x820*/
150 	u32 pw_mtcmos_en0;	/*0x830*/
158 	u32 pw_stat0;		/*0x850*/
163 	u32 systest_stat;	/*0x880*/
167 	u32 systest_slicer_cnt0;/*0x890*/
172 	u32 pw_ctrl1;		/*0x8C8*/
181 	u32 mcpu_vote_msk0;	/*0x8E0*/
186 	u32 peri_voteen;	/*0x8F0*/
192 	u32 peri_vote_msk0;	/*0x900*/
202 	u32 acpu_vote_msk0;	/*0x920*/
212 	u32 mcu_vote_msk0;	/*0x940*/
219 	u32 mcu_vote_vote1en;	/*0x960*/
225 	u32 mcu_vote_vote1_msk0;/*0x970*/
235 	u32 mcu_vote2_msk0;	/*0x990*/
240 	u32 vote_stat;		/*0x9a4*/
244 	u32 econum;		/*0xf00*/
248 	u32 scchipid;		/*0xf10*/
252 	u32 scsocid;		/*0xf1c*/
256 	u32 soc_fpga_rtl_def;	/*0xfe0*/
259 	u32 soc_fpga_res_def1;	/*0xfec*/
264 #define ALWAYSON_SC_SYS_CTRL0_MODE_NORMAL			0x004
265 #define ALWAYSON_SC_SYS_CTRL0_MODE_MASK				0x007
269 #define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG			(1 << 0)
319 #define ALWAYSON_SC_SYS_STAT1_MODE_STATUS			(1 << 0)
330 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3			0x003
331 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK			0x007
341 #define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_MCU			(1 << 0)
374 #define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU		(1 << 0)
385 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_ECTR_N		(1 << 0)