Lines Matching refs:u32
256 u32 porsr1; /* POR status 1 */
257 u32 porsr2; /* POR status 2 */
259 u32 gpporcr1; /* General-purpose POR configuration */
260 u32 gpporcr2; /* General-purpose POR configuration 2 */
261 u32 gpporcr3;
262 u32 gpporcr4;
273 u32 dcfg_fusesr; /* Fuse status register */
275 u32 devdisr; /* Device disable control 1 */
276 u32 devdisr2; /* Device disable control 2 */
277 u32 devdisr3; /* Device disable control 3 */
278 u32 devdisr4; /* Device disable control 4 */
279 u32 devdisr5; /* Device disable control 5 */
280 u32 devdisr6; /* Device disable control 6 */
282 u32 coredisr; /* Device disable control 7 */
308 u32 pvr; /* Processor version */
309 u32 svr; /* System version */
311 u32 rcwsr[30]; /* Reset control word status */
383 u32 scratchrw[16]; /* Scratch Read/Write */
385 u32 scratchw1r[4]; /* Scratch Read (Write once) */
387 u32 bootlocptrl; /* Boot location pointer low-order addr */
388 u32 bootlocptrh; /* Boot location pointer high-order addr */
390 u32 usb1_amqr;
391 u32 usb2_amqr;
393 u32 sdmm1_amqr;
395 u32 sata1_amqr;
396 u32 sata2_amqr;
398 u32 misc1_amqr;
400 u32 spare1_amqr;
401 u32 spare2_amqr;
403 u32 gencr[7]; /* General Control Registers */
405 u32 cgensr1; /* Core General Status Register */
407 u32 cgencr1; /* Core General Control Register */
409 u32 tp_ityp[64]; /* Topology Initiator Type Register */
411 u32 upper;
412 u32 lower;
415 u32 ioqoscr[8]; /*I/O Quality of Services Register */
416 u32 uccr;
418 u32 ftmcr;
420 u32 coredisablesr;
422 u32 sdbgcr; /*Secure Debug Confifuration Register */
424 u32 ipbrr1;
425 u32 ipbrr2;
432 u32 csr;
437 u32 gsr;
445 u32 csr; /* core cluster n clock control status */
451 u32 rstcr; /* 0x000 */
452 u32 rstcrsp; /* 0x004 */
454 u32 rstrqmr1; /* 0x010 */
455 u32 rstrqmr2; /* 0x014 */
456 u32 rstrqsr1; /* 0x018 */
457 u32 rstrqsr2; /* 0x01c */
458 u32 rstrqwdtmrl; /* 0x020 */
459 u32 rstrqwdtmru; /* 0x024 */
461 u32 rstrqwdtsrl; /* 0x030 */
462 u32 rstrqwdtsru; /* 0x034 */
464 u32 brrl; /* 0x060 */
465 u32 brru; /* 0x064 */
467 u32 pirset; /* 0x080 */
468 u32 pirclr; /* 0x084 */
470 u32 brcorenbr; /* 0x090 */
472 u32 rcw_reqr; /* 0x100 */
473 u32 rcw_completion; /* 0x104 */
475 u32 pbi_reqr; /* 0x110 */
476 u32 pbi_completion; /* 0x114 */
478 u32 qmbm_warmrst; /* 0xa00 */
479 u32 soc_warmrst; /* 0xa04 */
481 u32 ip_rev1; /* 0xbf8 */
482 u32 ip_rev2; /* 0xbfc */
487 u32 rstctl; /* Reset Control Register */
488 u32 pllcr0; /* PLL Control Register 0 */
489 u32 pllcr1; /* PLL Control Register 1 */
490 u32 pllcr2; /* PLL Control Register 2 */
491 u32 pllcr3; /* PLL Control Register 3 */
492 u32 pllcr4; /* PLL Control Register 4 */
493 u32 pllcr5; /* PLL Control Register 5 */
497 u32 srdstcalcr; /* TX Calibration Control */
498 u32 srdstcalcr1; /* TX Calibration Control1 */
500 u32 srdsrcalcr; /* RX Calibration Control */
501 u32 srdsrcalcr1; /* RX Calibration Control1 */
503 u32 srdsgr0; /* General Register 0 */
506 u32 gcr0; /* General Control Register 0 */
507 u32 gcr1; /* General Control Register 1 */
508 u32 gcr2; /* General Control Register 2 */
509 u32 ssc0; /* Speed Switch Control 0 */
510 u32 rec0; /* Receive Equalization Control 0 */
511 u32 rec1; /* Receive Equalization Control 1 */
512 u32 tec0; /* Transmit Equalization Control 0 */
513 u32 ssc1; /* Speed Switch Control 1 */