Lines Matching defs:ccsr_gur
255 struct ccsr_gur { struct
256 u32 porsr1; /* POR status 1 */
257 u32 porsr2; /* POR status 2 */
258 u8 res_008[0x20-0x8];
259 u32 gpporcr1; /* General-purpose POR configuration */
260 u32 gpporcr2; /* General-purpose POR configuration 2 */
261 u32 gpporcr3;
262 u32 gpporcr4;
263 u8 res_030[0x60-0x30];
273 u32 dcfg_fusesr; /* Fuse status register */
274 u8 res_064[0x70-0x64];
275 u32 devdisr; /* Device disable control 1 */
276 u32 devdisr2; /* Device disable control 2 */
277 u32 devdisr3; /* Device disable control 3 */
278 u32 devdisr4; /* Device disable control 4 */
279 u32 devdisr5; /* Device disable control 5 */
280 u32 devdisr6; /* Device disable control 6 */
281 u8 res_088[0x94-0x88];
282 u32 coredisr; /* Device disable control 7 */
307 u8 res_098[0xa0-0x98];
308 u32 pvr; /* Processor version */
309 u32 svr; /* System version */
310 u8 res_0a8[0x100-0xa8];
311 u32 rcwsr[30]; /* Reset control word status */
382 u8 res_178[0x200-0x178];
383 u32 scratchrw[16]; /* Scratch Read/Write */
384 u8 res_240[0x300-0x240];
385 u32 scratchw1r[4]; /* Scratch Read (Write once) */
386 u8 res_310[0x400-0x310];
387 u32 bootlocptrl; /* Boot location pointer low-order addr */
388 u32 bootlocptrh; /* Boot location pointer high-order addr */
389 u8 res_408[0x520-0x408];
390 u32 usb1_amqr;
391 u32 usb2_amqr;
392 u8 res_528[0x530-0x528]; /* add more registers when needed */
393 u32 sdmm1_amqr;
394 u8 res_534[0x550-0x534]; /* add more registers when needed */
395 u32 sata1_amqr;
396 u32 sata2_amqr;
397 u8 res_558[0x570-0x558]; /* add more registers when needed */
398 u32 misc1_amqr;
399 u8 res_574[0x590-0x574]; /* add more registers when needed */
400 u32 spare1_amqr;
401 u32 spare2_amqr;
402 u8 res_598[0x620-0x598]; /* add more registers when needed */
403 u32 gencr[7]; /* General Control Registers */
404 u8 res_63c[0x640-0x63c]; /* add more registers when needed */
405 u32 cgensr1; /* Core General Status Register */
406 u8 res_644[0x660-0x644]; /* add more registers when needed */
407 u32 cgencr1; /* Core General Control Register */
408 u8 res_664[0x740-0x664]; /* add more registers when needed */
409 u32 tp_ityp[64]; /* Topology Initiator Type Register */
410 struct {
413 } tp_cluster[4]; /* Core cluster n Topology Register */
414 u8 res_864[0x920-0x864]; /* add more registers when needed */
415 u32 ioqoscr[8]; /*I/O Quality of Services Register */
416 u32 uccr;
417 u8 res_944[0x960-0x944]; /* add more registers when needed */
418 u32 ftmcr;
419 u8 res_964[0x990-0x964]; /* add more registers when needed */
420 u32 coredisablesr;
421 u8 res_994[0xa00-0x994]; /* add more registers when needed */
422 u32 sdbgcr; /*Secure Debug Confifuration Register */
423 u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */
424 u32 ipbrr1;
425 u32 ipbrr2;
426 u8 res_858[0x1000-0xc00];