Lines Matching defs:ccsr_serdes
554 struct ccsr_serdes { struct
555 struct {
588 } bank[2];
589 u8 res_40[0x90-0x40];
590 u32 srdstcalcr; /* 0x90 TX Calibration Control */
591 u8 res_94[0xa0-0x94];
592 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
593 u8 res_a4[0xb0-0xa4];
594 u32 srdsgr0; /* 0xb0 General Register 0 */
595 u8 res_b4[0x100-0xb4];
596 struct {
599 } lnpssr[4]; /* Lane A, B, C, D */
600 u8 res_180[0x200-0x180];
601 u32 srdspccr0; /* 0x200 Protocol Configuration 0 */
602 u32 srdspccr1; /* 0x204 Protocol Configuration 1 */
603 u32 srdspccr2; /* 0x208 Protocol Configuration 2 */
604 u32 srdspccr3; /* 0x20c Protocol Configuration 3 */
605 u32 srdspccr4; /* 0x210 Protocol Configuration 4 */
606 u32 srdspccr5; /* 0x214 Protocol Configuration 5 */
607 u32 srdspccr6; /* 0x218 Protocol Configuration 6 */
608 u32 srdspccr7; /* 0x21c Protocol Configuration 7 */
609 u32 srdspccr8; /* 0x220 Protocol Configuration 8 */
610 u32 srdspccr9; /* 0x224 Protocol Configuration 9 */
611 u32 srdspccra; /* 0x228 Protocol Configuration A */
612 u32 srdspccrb; /* 0x22c Protocol Configuration B */
613 u8 res_230[0x800-0x230];
614 struct {
626 } lane[4]; /* Lane A, B, C, D */
627 u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */
628 struct {
631 } pcie[3];
632 u8 res_10c0[0x1800-0x10c0];
633 struct {
638 } sgmii[4]; /* Lane A, B, C, D */
639 u8 res_1840[0x1880-0x1840];
640 struct {
645 } qsgmii[2]; /* Lane A, B */
646 u8 res_18a0[0x1980-0x18a0];
647 struct {
652 } xfi[2]; /* Lane A, B */
653 u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */