Lines Matching defs:ccsr_gur
224 struct ccsr_gur { struct
225 u32 porsr1; /* POR status 1 */
227 u32 porsr2; /* POR status 2 */
228 u8 res_008[0x20-0x8];
229 u32 gpporcr1; /* General-purpose POR configuration */
230 u32 gpporcr2;
235 u32 dcfg_fusesr; /* Fuse status register */
236 u8 res_02c[0x70-0x2c];
237 u32 devdisr; /* Device disable control */
250 u32 devdisr2; /* Device disable control 2 */
251 u32 devdisr3; /* Device disable control 3 */
252 u32 devdisr4; /* Device disable control 4 */
253 u32 devdisr5; /* Device disable control 5 */
254 u32 devdisr6; /* Device disable control 6 */
255 u32 devdisr7; /* Device disable control 7 */
256 u8 res_08c[0x94-0x8c];
257 u32 coredisru; /* uppper portion for support of 64 cores */
258 u32 coredisrl; /* lower portion for support of 64 cores */
259 u8 res_09c[0xa0-0x9c];
260 u32 pvr; /* Processor version */
261 u32 svr; /* System version */
262 u32 mvr; /* Manufacturing version */
263 u8 res_0ac[0xb0-0xac];
264 u32 rstcr; /* Reset control */
265 u32 rstrqpblsr; /* Reset request preboot loader status */
266 u8 res_0b8[0xc0-0xb8];
267 u32 rstrqmr1; /* Reset request mask */
268 u8 res_0c4[0xc8-0xc4];
269 u32 rstrqsr1; /* Reset request status */
270 u8 res_0cc[0xd4-0xcc];
271 u32 rstrqwdtmrl; /* Reset request WDT mask */
272 u8 res_0d8[0xdc-0xd8];
273 u32 rstrqwdtsrl; /* Reset request WDT status */
274 u8 res_0e0[0xe4-0xe0];
275 u32 brrl; /* Boot release */
276 u8 res_0e8[0x100-0xe8];
277 u32 rcwsr[16]; /* Reset control word status */
289 u8 res_140[0x200-0x140];
290 u32 scratchrw[4]; /* Scratch Read/Write */
291 u8 res_210[0x300-0x210];
292 u32 scratchw1r[4]; /* Scratch Read (Write once) */
293 u8 res_310[0x400-0x310];
294 u32 crstsr[12];
295 u8 res_430[0x500-0x430];
298 u32 dcfg_ccsr_pex1liodnr;
299 u32 dcfg_ccsr_pex2liodnr;
300 u32 dcfg_ccsr_pex3liodnr;
301 u32 dcfg_ccsr_pex4liodnr;
303 u32 dcfg_ccsr_rio1liodnr;
304 u32 dcfg_ccsr_rio2liodnr;
305 u32 dcfg_ccsr_rio3liodnr;
306 u32 dcfg_ccsr_rio4liodnr;
308 u32 dcfg_ccsr_usb1liodnr;
309 u32 dcfg_ccsr_usb2liodnr;
310 u32 dcfg_ccsr_usb3liodnr;
311 u32 dcfg_ccsr_usb4liodnr;
313 u32 dcfg_ccsr_sdmmc1liodnr;
314 u32 dcfg_ccsr_sdmmc2liodnr;
315 u32 dcfg_ccsr_sdmmc3liodnr;
316 u32 dcfg_ccsr_sdmmc4liodnr;
318 u32 dcfg_ccsr_riomaintliodnr;
320 u8 res_544[0x550-0x544];
321 u32 sataliodnr[4];
322 u8 res_560[0x570-0x560];
324 u32 dcfg_ccsr_misc1liodnr;
325 u32 dcfg_ccsr_misc2liodnr;
326 u32 dcfg_ccsr_misc3liodnr;
327 u32 dcfg_ccsr_misc4liodnr;
328 u32 dcfg_ccsr_dma1liodnr;
329 u32 dcfg_ccsr_dma2liodnr;
330 u32 dcfg_ccsr_dma3liodnr;
331 u32 dcfg_ccsr_dma4liodnr;
332 u32 dcfg_ccsr_spare1liodnr;
333 u32 dcfg_ccsr_spare2liodnr;
334 u32 dcfg_ccsr_spare3liodnr;
335 u32 dcfg_ccsr_spare4liodnr;
336 u8 res_5a0[0x600-0x5a0];
337 u32 dcfg_ccsr_pblsr;
339 u32 pamubypenr;
340 u32 dmacr1;
342 u8 res_60c[0x610-0x60c];
343 u32 dcfg_ccsr_gensr1;
344 u32 dcfg_ccsr_gensr2;
345 u32 dcfg_ccsr_gensr3;
346 u32 dcfg_ccsr_gensr4;
347 u32 dcfg_ccsr_gencr1;
348 u32 dcfg_ccsr_gencr2;
349 u32 dcfg_ccsr_gencr3;
350 u32 dcfg_ccsr_gencr4;
351 u32 dcfg_ccsr_gencr5;
352 u32 dcfg_ccsr_gencr6;
353 u32 dcfg_ccsr_gencr7;
354 u8 res_63c[0x658-0x63c];
355 u32 dcfg_ccsr_cgensr1;
356 u32 dcfg_ccsr_cgensr0;
357 u8 res_660[0x678-0x660];
358 u32 dcfg_ccsr_cgencr1;
360 u32 dcfg_ccsr_cgencr0;
361 u8 res_680[0x700-0x680];
362 u32 dcfg_ccsr_sriopstecr;
363 u32 dcfg_ccsr_dcsrcr;
365 u8 res_708[0x740-0x708]; /* add more registers when needed */
366 u32 tp_ityp[64]; /* Topology Initiator Type Register */
367 struct {
370 } tp_cluster[16];
371 u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */
372 u32 dcfg_ccsr_qmbm_warmrst;
373 u8 res_a04[0xa20-0xa04]; /* add more registers when needed */
374 u32 dcfg_ccsr_reserved0;
375 u32 dcfg_ccsr_reserved1;