Lines Matching +full:0 +full:x80820000
24 #define EP93XX_AHB_BASE 0x80000000
25 #define EP93XX_APB_BASE 0x80800000
28 * 0x80000000 - 0x8000FFFF: DMA
30 #define DMA_OFFSET 0x000000
73 * 0x80010000 - 0x8001FFFF: Ethernet MAC
75 #define MAC_OFFSET 0x010000
155 #define SELFCTL_RESET (1 << 0)
186 #define BMCTL_RXEN (1 << 0)
191 #define BMSTS_QID_MASK 0x07
192 #define BMSTS_QID_RXDATA 0x00
193 #define BMSTS_QID_TXDATA 0x01
194 #define BMSTS_QID_RXSTS 0x02
195 #define BMSTS_QID_TXSTS 0x03
196 #define BMSTS_QID_RXDESC 0x04
197 #define BMSTS_QID_TXDESC 0x05
199 #define AFP_MASK 0x07
200 #define AFP_IAPRIMARY 0x00
201 #define AFP_IASECONDARY1 0x01
202 #define AFP_IASECONDARY2 0x02
203 #define AFP_IASECONDARY3 0x03
204 #define AFP_TX 0x06
205 #define AFP_HASH 0x07
221 #define RXCTL_IA0 (1 << 0)
230 #define TXCTL_STXON (1 << 0)
232 #define MIICMD_REGAD_MASK (0x001F)
233 #define MIICMD_PHYAD_MASK (0x03E0)
234 #define MIICMD_OPCODE_MASK (0xC000)
235 #define MIICMD_PHYAD_8950 (0x0000)
236 #define MIICMD_OPCODE_READ (0x8000)
237 #define MIICMD_OPCODE_WRITE (0x4000)
239 #define MIISTS_BUSY (1 << 0)
242 * 0x80020000 - 0x8002FFFF: USB OHCI
244 #define USB_OFFSET 0x020000
248 * 0x80030000 - 0x8003FFFF: Raster engine
251 #define RASTER_OFFSET 0x030000
256 * 0x80040000 - 0x8004FFFF: Graphics accelerator
259 #define GFX_OFFSET 0x040000
264 * 0x80050000 - 0x8005FFFF: Reserved
268 * 0x80060000 - 0x8006FFFF: SDRAM controller
270 #define SDRAM_OFFSET 0x060000
289 #define SDRAM_DEVCFG_CASLAT_2 0x00010000
290 #define SDRAM_DEVCFG_RASTOCAS_2 0x00200000
292 #define SDRAM_OFF_GLCONFIG 0x0004
293 #define SDRAM_OFF_REFRSHTIMR 0x0008
295 #define SDRAM_OFF_DEVCFG0 0x0010
296 #define SDRAM_OFF_DEVCFG1 0x0014
297 #define SDRAM_OFF_DEVCFG2 0x0018
298 #define SDRAM_OFF_DEVCFG3 0x001C
300 #define SDRAM_DEVCFG0_BASE 0xC0000000
301 #define SDRAM_DEVCFG1_BASE 0xD0000000
302 #define SDRAM_DEVCFG2_BASE 0xE0000000
303 #define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000
304 #define SDRAM_DEVCFG3_ASD1_BASE 0x00000000
306 #define GLCONFIG_INIT (1 << 0)
314 #define EP93XX_SDRAMCTRL 0x80060000
315 #define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001
316 #define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002
317 #define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020
318 #define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040
319 #define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080
320 #define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000
321 #define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000
323 #define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF
325 #define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002
326 #define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001
327 #define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000
328 #define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003
329 #define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004
331 #define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004
332 #define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008
333 #define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010
334 #define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020
335 #define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040
336 #define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080
337 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000
338 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000
339 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000
340 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000
341 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000
342 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000
343 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000
344 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000
345 #define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000
346 #define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000
347 #define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000
348 #define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000
349 #define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000
352 * 0x80070000 - 0x8007FFFF: Reserved
356 * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
358 #define SMC_OFFSET 0x080000
380 #define EP93XX_OFF_SMCBCR0 0x00
381 #define EP93XX_OFF_SMCBCR1 0x04
382 #define EP93XX_OFF_SMCBCR2 0x08
383 #define EP93XX_OFF_SMCBCR3 0x0C
384 #define EP93XX_OFF_SMCBCR6 0x18
385 #define EP93XX_OFF_SMCBCR7 0x1C
387 #define SMC_BCR_IDCY_SHIFT 0
394 * 0x80090000 - 0x8009FFFF: Boot ROM
398 * 0x800A0000 - 0x800AFFFF: IDE interface
402 * 0x800B0000 - 0x800BFFFF: VIC1
406 * 0x800C0000 - 0x800CFFFF: VIC2
410 * 0x800D0000 - 0x800FFFFF: Reserved
414 * 0x80800000 - 0x8080FFFF: Reserved
418 * 0x80810000 - 0x8081FFFF: Timers
420 #define TIMER_OFFSET 0x010000
448 * 0x80820000 - 0x8082FFFF: I2S
450 #define I2S_OFFSET 0x020000
454 * 0x80830000 - 0x8083FFFF: Security
456 #define SECURITY_OFFSET 0x030000
459 #define EXTENSIONID (SECURITY_BASE + 0x2714)
462 * 0x80840000 - 0x8084FFFF: GPIO
464 #define GPIO_OFFSET 0x040000
508 #define EP93XX_LED_DATA 0x80840020
509 #define EP93XX_LED_GREEN_ON 0x0001
510 #define EP93XX_LED_RED_ON 0x0002
512 #define EP93XX_LED_DDR 0x80840024
513 #define EP93XX_LED_GREEN_ENABLE 0x0001
514 #define EP93XX_LED_RED_ENABLE 0x00020000
517 * 0x80850000 - 0x8087FFFF: Reserved
521 * 0x80880000 - 0x8088FFFF: AAC
523 #define AAC_OFFSET 0x080000
527 * 0x80890000 - 0x8089FFFF: Reserved
531 * 0x808A0000 - 0x808AFFFF: SPI
533 #define SPI_OFFSET 0x0A0000
537 * 0x808B0000 - 0x808BFFFF: IrDA
539 #define IRDA_OFFSET 0x0B0000
543 * 0x808C0000 - 0x808CFFFF: UART1
545 #define UART1_OFFSET 0x0C0000
549 * 0x808D0000 - 0x808DFFFF: UART2
551 #define UART2_OFFSET 0x0D0000
555 * 0x808E0000 - 0x808EFFFF: UART3
557 #define UART3_OFFSET 0x0E0000
561 * 0x808F0000 - 0x808FFFFF: Key Matrix
563 #define KEY_OFFSET 0x0F0000
567 * 0x80900000 - 0x8090FFFF: Touchscreen
569 #define TOUCH_OFFSET 0x900000
573 * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
575 #define PWM_OFFSET 0x910000
579 * 0x80920000 - 0x8092FFFF: Real time clock
581 #define RTC_OFFSET 0x920000
585 * 0x80930000 - 0x8093FFFF: Syscon
587 #define SYSCON_OFFSET 0x930000
591 #define SECURITY_EXTENSIONID 0x80832714
624 #define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040)
627 #define SYSCON_OFF_CLKSET1 0x0020
628 #define SYSCON_OFF_SYSCFG 0x009c
633 #define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0
646 #define SYSCON_CHIPID_REV_MASK 0xF0000000
649 #define SYSCON_SYSCFG_LASDO 0x00000020
652 * 0x80930000 - 0x8093FFFF: Watchdog Timer
654 #define WATCHDOG_OFFSET 0x940000
658 * 0x80950000 - 0x9000FFFF: Reserved
664 #define UBOOT_MEMORYCNF_BANK_SIZE 0x2000
665 #define UBOOT_MEMORYCNF_BANK_MASK 0x2004
666 #define UBOOT_MEMORYCNF_BANK_COUNT 0x2008