Lines Matching +full:0 +full:x45

9 #define BOOT_DEVICE_NONE	0x00
10 #define BOOT_DEVICE_MMC2_2	0xFF
13 #define BOOT_DEVICE_XIP		0x01
14 #define BOOT_DEVICE_XIPWAIT	0x02
15 #define BOOT_DEVICE_NAND	0x05
16 #define BOOT_DEVICE_NAND_I2C	0x06
17 #define BOOT_DEVICE_MMC2	0x08 /* ROM only supports 2nd instance. */
18 #define BOOT_DEVICE_MMC1	0x09
19 #define BOOT_DEVICE_SPI		0x15
20 #define BOOT_DEVICE_UART	0x41
21 #define BOOT_DEVICE_USBETH	0x44
22 #define BOOT_DEVICE_CPGMAC	0x46
27 #define BOOT_DEVICE_XIP		0x01
28 #define BOOT_DEVICE_XIPWAIT	0x02
29 #define BOOT_DEVICE_NAND	0x03
30 #define BOOT_DEVICE_ONENAND	0x04
31 #define BOOT_DEVICE_MMC2	0x05 /* ROM only supports 2nd instance. */
32 #define BOOT_DEVICE_MMC1	0x06
33 #define BOOT_DEVICE_UART	0x43
34 #define BOOT_DEVICE_USB		0x45
39 #define BOOT_DEVICE_XIP		0x01
40 #define BOOT_DEVICE_XIPWAIT	0x02
41 #define BOOT_DEVICE_NAND	0x05
42 #define BOOT_DEVICE_NAND_I2C	0x06
43 #define BOOT_DEVICE_MMC1	0x08
44 #define BOOT_DEVICE_MMC2	0x09
45 #define BOOT_DEVICE_SPI		0x0B
46 #define BOOT_DEVICE_UART	0x41
47 #define BOOT_DEVICE_USBETH	0x44
48 #define BOOT_DEVICE_CPGMAC	0x46
49 #define BOOT_DEVICE_ONENAND	0xFF /* ROM does not support OneNAND. */
54 #define BOOT_DEVICE_NOR		0x01
55 #define BOOT_DEVICE_NAND	0x05
56 #define BOOT_DEVICE_MMC1	0x07
57 #define BOOT_DEVICE_MMC2	0x08
58 #define BOOT_DEVICE_SPI		0x0A
59 #define BOOT_DEVICE_USB		0x0D
60 #define BOOT_DEVICE_UART	0x41
61 #define BOOT_DEVICE_USBETH	0x45
62 #define BOOT_DEVICE_CPGMAC	0x47