Lines Matching +full:0 +full:x84
17 #define VTP_CTRL_READY (0x1 << 5)
18 #define VTP_CTRL_ENABLE (0x1 << 6)
19 #define VTP_CTRL_START_EN (0x1)
21 #define DDR_CKE_CTRL_NORMAL 0x3
23 #define DDR_CKE_CTRL_NORMAL 0x1
25 #define PHY_EN_DYN_PWRDN (0x1 << 20)
28 #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
29 #define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
30 #define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
31 #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
32 #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
33 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
34 #define MT47H128M16RT25E_RATIO 0x80
35 #define MT47H128M16RT25E_RD_DQS 0x12
36 #define MT47H128M16RT25E_PHY_WR_DATA 0x40
37 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80
38 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
41 #define MT41J128MJT125_EMIF_READ_LATENCY 0x100006
42 #define MT41J128MJT125_EMIF_TIM1 0x0888A39B
43 #define MT41J128MJT125_EMIF_TIM2 0x26337FDA
44 #define MT41J128MJT125_EMIF_TIM3 0x501F830F
45 #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
46 #define MT41J128MJT125_EMIF_SDREF 0x0000093B
47 #define MT41J128MJT125_ZQ_CFG 0x50074BE4
48 #define MT41J128MJT125_RATIO 0x40
49 #define MT41J128MJT125_INVERT_CLKOUT 0x1
50 #define MT41J128MJT125_RD_DQS 0x3B
51 #define MT41J128MJT125_WR_DQS 0x85
52 #define MT41J128MJT125_PHY_WR_DATA 0xC1
53 #define MT41J128MJT125_PHY_FIFO_WE 0x100
54 #define MT41J128MJT125_IOCTRL_VALUE 0x18B
57 #define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007
58 #define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB
59 #define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA
60 #define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF
61 #define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2
62 #define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30
63 #define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4
64 #define MT41J128MJT125_RATIO_400MHz 0x80
65 #define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0
66 #define MT41J128MJT125_RD_DQS_400MHz 0x3A
67 #define MT41J128MJT125_WR_DQS_400MHz 0x3B
68 #define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76
69 #define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96
72 #define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
73 #define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
74 #define MT41K128MJT187E_EMIF_TIM2 0x36337FDA
75 #define MT41K128MJT187E_EMIF_TIM3 0x501F830F
76 #define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2
77 #define MT41K128MJT187E_EMIF_SDREF 0x0000093B
78 #define MT41K128MJT187E_ZQ_CFG 0x50074BE4
79 #define MT41K128MJT187E_RATIO 0x40
80 #define MT41K128MJT187E_INVERT_CLKOUT 0x1
81 #define MT41K128MJT187E_RD_DQS 0x3B
82 #define MT41K128MJT187E_WR_DQS 0x85
83 #define MT41K128MJT187E_PHY_WR_DATA 0xC1
84 #define MT41K128MJT187E_PHY_FIFO_WE 0x100
85 #define MT41K128MJT187E_IOCTRL_VALUE 0x18B
88 #define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
91 #define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
94 #define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006
95 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
96 #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
97 #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
98 #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
99 #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
100 #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
101 #define MT41J256M8HX15E_RATIO 0x40
102 #define MT41J256M8HX15E_INVERT_CLKOUT 0x1
103 #define MT41J256M8HX15E_RD_DQS 0x3B
104 #define MT41J256M8HX15E_WR_DQS 0x85
105 #define MT41J256M8HX15E_PHY_WR_DATA 0xC1
106 #define MT41J256M8HX15E_PHY_FIFO_WE 0x100
107 #define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
110 #define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
111 #define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
112 #define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
113 #define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
114 #define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
115 #define MT41K256M16HA125E_EMIF_SDREF 0xC30
116 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
117 #define MT41K256M16HA125E_RATIO 0x80
118 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0
119 #define MT41K256M16HA125E_RD_DQS 0x38
120 #define MT41K256M16HA125E_WR_DQS 0x44
121 #define MT41K256M16HA125E_PHY_WR_DATA 0x7D
122 #define MT41K256M16HA125E_PHY_FIFO_WE 0x94
123 #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
126 #define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006
127 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
128 #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
129 #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
130 #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
131 #define MT41J512M8RH125_EMIF_SDREF 0x0000093B
132 #define MT41J512M8RH125_ZQ_CFG 0x50074BE4
133 #define MT41J512M8RH125_RATIO 0x80
134 #define MT41J512M8RH125_INVERT_CLKOUT 0x0
135 #define MT41J512M8RH125_RD_DQS 0x3B
136 #define MT41J512M8RH125_WR_DQS 0x3C
137 #define MT41J512M8RH125_PHY_FIFO_WE 0xA5
138 #define MT41J512M8RH125_PHY_WR_DATA 0x74
139 #define MT41J512M8RH125_IOCTRL_VALUE 0x18B
142 #define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007
143 #define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
144 #define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
145 #define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
146 #define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
147 #define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
148 #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
149 #define K4B2G1646EBIH9_RATIO 0x80
150 #define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
151 #define K4B2G1646EBIH9_RD_DQS 0x35
152 #define K4B2G1646EBIH9_WR_DQS 0x3A
153 #define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
154 #define K4B2G1646EBIH9_PHY_WR_DATA 0x76
155 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
157 #define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294
158 #define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
159 #define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
160 #define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294
161 #define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294
162 #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
163 #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
165 #define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
166 #define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
167 #define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
168 #define DDR3_DATA0_IOCTRL_VALUE 0x84
169 #define DDR3_DATA1_IOCTRL_VALUE 0x84
170 #define DDR3_DATA2_IOCTRL_VALUE 0x84
171 #define DDR3_DATA3_IOCTRL_VALUE 0x84
196 unsigned int cm0csratio; /* offset 0x01C */
198 unsigned int cm0iclkout; /* offset 0x02C */
200 unsigned int cm1csratio; /* offset 0x050 */
202 unsigned int cm1iclkout; /* offset 0x060 */
204 unsigned int cm2csratio; /* offset 0x084 */
206 unsigned int cm2iclkout; /* offset 0x094 */
211 unsigned int dt0rdsratio0; /* offset 0x0C8 */
213 unsigned int dt0wdsratio0; /* offset 0x0DC */
215 unsigned int dt0wiratio0; /* offset 0x0F0 */
217 unsigned int dt0wimode0; /* offset 0x0F8 */
218 unsigned int dt0giratio0; /* offset 0x0FC */
220 unsigned int dt0gimode0; /* offset 0x104 */
221 unsigned int dt0fwsratio0; /* offset 0x108 */
223 unsigned int dt0dqoffset; /* offset 0x11C */
224 unsigned int dt0wrsratio0; /* offset 0x120 */
226 unsigned int dt0rdelays0; /* offset 0x134 */
227 unsigned int dt0dldiff0; /* offset 0x138 */
238 unsigned int cm0config; /* offset 0x00C */
239 unsigned int cm0configclk; /* offset 0x010 */
241 unsigned int cm0csratio; /* offset 0x01C */
243 unsigned int cm0iclkout; /* offset 0x02C */
245 unsigned int cm1config; /* offset 0x040 */
246 unsigned int cm1configclk; /* offset 0x044 */
248 unsigned int cm1csratio; /* offset 0x050 */
250 unsigned int cm1iclkout; /* offset 0x060 */
252 unsigned int cm2config; /* offset 0x074 */
253 unsigned int cm2configclk; /* offset 0x078 */
255 unsigned int cm2csratio; /* offset 0x084 */
257 unsigned int cm2iclkout; /* offset 0x094 */
259 unsigned int dt0rdsratio0; /* offset 0x0C8 */
261 unsigned int dt0wdsratio0; /* offset 0x0DC */
263 unsigned int dt0wiratio0; /* offset 0x0F0 */
265 unsigned int dt0wimode0; /* offset 0x0F8 */
266 unsigned int dt0giratio0; /* offset 0x0FC */
268 unsigned int dt0gimode0; /* offset 0x104 */
269 unsigned int dt0fwsratio0; /* offset 0x108 */
271 unsigned int dt0dqoffset; /* offset 0x11C */
272 unsigned int dt0wrsratio0; /* offset 0x120 */
274 unsigned int dt0rdelays0; /* offset 0x134 */
275 unsigned int dt0dldiff0; /* offset 0x138 */