arm/dts/zynqmp-zcu104-revA.dts

1 // SPDX-License-Identifier: GPL-2.0+
5  * (C) Copyright 2017 - 2018, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/phy/phy.h>
19 	compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
36 		stdout-path = "serial0:115200n8";
55 	phy-handle = <&phy0>;
56 	phy-mode = "rgmii-id";
59 		ti,rx-internal-delay = <0x8>;
60 		ti,tx-internal-delay = <0xa>;
61 		ti,fifo-depth = <0x1>;
75 	clock-frequency = <400000>;
77 	/* Another connection to this bus via PL i2c via PCA9306 - u45 */
78 	i2c-mux@74 { /* u34 */
80 		#address-cells = <1>;
81 		#size-cells = <0>;
84 			#address-cells = <1>;
85 			#size-cells = <0>;
90 			 *    0 - 256B address 0x54
91 			 * 256B - 512B address 0x55
92 			 * 512B - 768B address 0x56
93 			 * 768B - 1024B address 0x57
98 				#address-cells = <1>;
99 				#size-cells = <1>;
104 			#address-cells = <1>;
105 			#size-cells = <0>;
107 			clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
114 			#address-cells = <1>;
115 			#size-cells = <0>;
117 			irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
118 				#clock-cells = <0>;
122 			irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
123 				#clock-cells = <0>;
130 			#address-cells = <1>;
131 			#size-cells = <0>;
136 				gpio-controller;
137 				#gpio-cells = <2>;
141 				 * 0 - IRPS5401_ALERT_B
142 				 * 1 - HDMI_8T49N241_INT_ALM
143 				 * 2 - MAX6643_OT_B
144 				 * 3 - MAX6643_FANFAIL_B
145 				 * 5 - IIC_MUX_RESET_B
146 				 * 6 - GEM3_EXP_RESET_B
147 				 * 7 - FMC_LPC_PRSNT_M2C_B
148 				 * 4, 10 - 17 - not connected
154 			#address-cells = <1>;
155 			#size-cells = <0>;
160 			#address-cells = <1>;
161 			#size-cells = <0>;
172 		compatible = "m25p80", "spi-flash"; /* n25q512a 128MiB */
173 		#address-cells = <1>;
174 		#size-cells = <1>;
176 		spi-tx-bus-width = <1>;
177 		spi-rx-bus-width = <4>;
178 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
179 		partition@qspi-fsbl-uboot { /* for testing purpose */
180 			label = "qspi-fsbl-uboot";
183 		partition@qspi-linux { /* for testing purpose */
184 			label = "qspi-linux";
187 		partition@qspi-device-tree { /* for testing purpose */
188 			label = "qspi-device-tree";
191 		partition@qspi-rootfs { /* for testing purpose */
192 			label = "qspi-rootfs";
205 	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
206 	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
207 	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
208 	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
209 	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
210 	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
211 	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
212 	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
213 	phy-names = "sata-phy";
220 	no-1-8-v;
222 	disable-wp;
246 	phy-names = "usb3-phy";
248 	maximum-speed = "super-speed";