Lines Matching +full:dp +full:- +full:phy0
1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
20 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
47 gpio-keys {
48 compatible = "gpio-keys";
54 gpio-key,wakeup;
60 compatible = "gpio-leds";
64 linux,default-trigger = "heartbeat";
111 phy-handle = <&phy0>;
112 phy-mode = "rgmii-id";
113 phy0: phy@21 { label
115 ti,rx-internal-delay = <0x8>;
116 ti,tx-internal-delay = <0xa>;
117 ti,fifo-depth = <0x1>;
131 clock-frequency = <400000>;
136 gpio-controller;
137 #gpio-cells = <2>;
141 * 0 - PS_GTR_LAN_SEL0
142 * 1 - PS_GTR_LAN_SEL1
143 * 2 - PS_GTR_LAN_SEL2
144 * 3 - PS_GTR_LAN_SEL3
145 * 4 - PCI_CLK_DIR_SEL
146 * 5 - IIC_MUX_RESET_B
147 * 6 - GEM3_EXP_RESET_B
148 * 7, 10 - 17 - not connected
152 gpio-hog;
154 output-low; /* PCIE = 0, DP = 1 */
155 line-name = "sel0";
158 gpio-hog;
160 output-high; /* PCIE = 0, DP = 1 */
161 line-name = "sel1";
164 gpio-hog;
166 output-high; /* PCIE = 0, USB0 = 1 */
167 line-name = "sel2";
170 gpio-hog;
172 output-high; /* PCIE = 0, SATA = 1 */
173 line-name = "sel3";
180 gpio-controller;
181 #gpio-cells = <2>;
185 * 0 - VCCPSPLL_EN
186 * 1 - MGTRAVCC_EN
187 * 2 - MGTRAVTT_EN
188 * 3 - VCCPSDDRPLL_EN
189 * 4 - MIO26_PMU_INPUT_LS
190 * 5 - PL_PMBUS_ALERT
191 * 6 - PS_PMBUS_ALERT
192 * 7 - MAXIM_PMBUS_ALERT
193 * 10 - PL_DDR4_VTERM_EN
194 * 11 - PL_DDR4_VPP_2V5_EN
195 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
196 * 13 - PS_DIMM_SUSPEND_EN
197 * 14 - PS_DDR4_VTERM_EN
198 * 15 - PS_DDR4_VPP_2V5_EN
199 * 16 - 17 - not connected
203 i2c-mux@75 { /* u60 */
205 #address-cells = <1>;
206 #size-cells = <0>;
209 #address-cells = <1>;
210 #size-cells = <0>;
216 shunt-resistor = <5000>;
221 shunt-resistor = <5000>;
226 shunt-resistor = <5000>;
231 shunt-resistor = <5000>;
236 shunt-resistor = <5000>;
241 shunt-resistor = <5000>;
246 shunt-resistor = <5000>;
251 shunt-resistor = <5000>;
256 shunt-resistor = <5000>;
261 shunt-resistor = <5000>;
265 #address-cells = <1>;
266 #size-cells = <0>;
272 shunt-resistor = <2000>;
277 shunt-resistor = <5000>;
282 shunt-resistor = <5000>;
287 shunt-resistor = <5000>;
292 shunt-resistor = <5000>;
297 shunt-resistor = <5000>;
302 shunt-resistor = <5000>;
307 shunt-resistor = <5000>;
311 #address-cells = <1>;
312 #size-cells = <0>;
314 /* MAXIM_PMBUS - 00 */
379 clock-frequency = <400000>;
381 /* PL i2c via PCA9306 - u45 */
382 i2c-mux@74 { /* u34 */
384 #address-cells = <1>;
385 #size-cells = <0>;
388 #address-cells = <1>;
389 #size-cells = <0>;
394 * 0 - 256B address 0x54
395 * 256B - 512B address 0x55
396 * 512B - 768B address 0x56
397 * 768B - 1024B address 0x57
405 #address-cells = <1>;
406 #size-cells = <0>;
408 si5341: clock-generator@36 { /* SI5341 - u69 */
415 #address-cells = <1>;
416 #size-cells = <0>;
418 si570_1: clock-generator@5d { /* USER SI570 - u42 */
419 #clock-cells = <0>;
422 temperature-stability = <50>;
423 factory-fout = <300000000>;
424 clock-frequency = <300000000>;
425 clock-output-names = "si570_user";
429 #address-cells = <1>;
430 #size-cells = <0>;
432 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
433 #clock-cells = <0>;
436 temperature-stability = <50>; /* copy from zc702 */
437 factory-fout = <156250000>;
438 clock-frequency = <148500000>;
439 clock-output-names = "si570_mgt";
443 #address-cells = <1>;
444 #size-cells = <0>;
446 si5328: clock-generator@69 {/* SI5328 - u20 */
451 * interrupt-parent = <&>;
456 /* 5 - 7 unconnected */
459 i2c-mux@75 {
461 #address-cells = <1>;
462 #size-cells = <0>;
466 #address-cells = <1>;
467 #size-cells = <0>;
472 #address-cells = <1>;
473 #size-cells = <0>;
478 #address-cells = <1>;
479 #size-cells = <0>;
484 #address-cells = <1>;
485 #size-cells = <0>;
490 #address-cells = <1>;
491 #size-cells = <0>;
496 #address-cells = <1>;
497 #size-cells = <0>;
502 #address-cells = <1>;
503 #size-cells = <0>;
508 #address-cells = <1>;
509 #size-cells = <0>;
522 is-dual = <1>;
524 compatible = "m25p80", "spi-flash"; /* 32MB */
525 #address-cells = <1>;
526 #size-cells = <1>;
528 spi-tx-bus-width = <1>;
529 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
530 spi-max-frequency = <108000000>; /* Based on DC1 spec */
531 partition@qspi-fsbl-uboot { /* for testing purpose */
532 label = "qspi-fsbl-uboot";
535 partition@qspi-linux { /* for testing purpose */
536 label = "qspi-linux";
539 partition@qspi-device-tree { /* for testing purpose */
540 label = "qspi-device-tree";
543 partition@qspi-rootfs { /* for testing purpose */
544 label = "qspi-rootfs";
557 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
558 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
559 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
560 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
561 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
562 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
563 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
564 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
565 phy-names = "sata-phy";
572 no-1-8-v; /* for 1.0 silicon */
597 phy-names = "usb3-phy";
599 maximum-speed = "super-speed";
629 xlnx,vid-clk-pl;