Lines Matching +full:zynqmp +full:- +full:8
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm016-dc2 RevA";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
35 stdout-path = "serial0:115200n8";
86 phy-handle = <&phy0>;
87 phy-mode = "rgmii-id";
90 ti,rx-internal-delay = <0x8>;
91 ti,tx-internal-delay = <0xa>;
92 ti,fifo-depth = <0x1>;
102 clock-frequency = <400000>;
107 gpio-controller;
108 #gpio-cells = <2>;
120 arasan,has-mdma;
121 num-cs = <2>;
124 label = "nand-fsbl-uboot";
128 label = "nand-linux";
132 label = "nand-device-tree";
136 label = "nand-rootfs";
140 label = "nand-bitstream";
144 label = "nand-misc";
149 label = "nand1-fsbl-uboot";
153 label = "nand1-linux";
156 partition@8 { /* for testing purpose */
157 label = "nand1-device-tree";
161 label = "nand1-rootfs";
165 label = "nand1-bitstream";
169 label = "nand1-misc";
180 num-cs = <1>;
182 #address-cells = <1>;
183 #size-cells = <1>;
184 compatible = "sst,sst25wf080", "jedec,spi-nor";
185 spi-max-frequency = <50000000>;
197 num-cs = <1>;
199 #address-cells = <1>;
200 #size-cells = <1>;
202 spi-max-frequency = <20000000>;