arm/dts/zynqmp-zc1751-xm015-dc1.dts

1 // SPDX-License-Identifier: GPL-2.0+
3  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 	model = "ZynqMP zc1751-xm015-dc1 RevA";
17 	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 		stdout-path = "serial0:115200n8";
76 	phy-handle = <&phy0>;
77 	phy-mode = "rgmii-id";
93 	clock-frequency = <400000>;
104 		compatible = "m25p80", "spi-flash"; /* Micron MT25QU512ABB8ESF */
105 		#address-cells = <1>;
106 		#size-cells = <1>;
108 		spi-tx-bus-width = <1>;
109 		spi-rx-bus-width = <4>;
110 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
111 		partition@qspi-fsbl-uboot { /* for testing purpose */
112 			label = "qspi-fsbl-uboot";
115 		partition@qspi-linux { /* for testing purpose */
116 			label = "qspi-linux";
119 		partition@qspi-device-tree { /* for testing purpose */
120 			label = "qspi-device-tree";
123 		partition@qspi-rootfs { /* for testing purpose */
124 			label = "qspi-rootfs";
137 	ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
138 	ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
139 	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
140 	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
141 	ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
142 	ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
143 	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
144 	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
150 	bus-width = <8>;
157 	no-1-8-v;       /* for 1.0 silicon */
185 	xlnx,vid-clk-pl;