Lines Matching +full:clock +full:- +full:frequency

1 // SPDX-License-Identifier: GPL-2.0+
3  * Clock specification for Xilinx ZynqMP
5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
12 		compatible = "fixed-clock";
13 		#clock-cells = <0>;
14 		clock-frequency = <100000000>;
15 		u-boot,dm-pre-reloc;
19 		compatible = "fixed-clock";
20 		#clock-cells = <0>;
21 		clock-frequency = <125000000>;
25 		compatible = "fixed-clock";
26 		#clock-cells = <0>;
27 		clock-frequency = <200000000>;
28 		u-boot,dm-pre-reloc;
32 		compatible = "fixed-clock";
33 		#clock-cells = <0>;
34 		clock-frequency = <250000000>;
38 		compatible = "fixed-clock";
39 		#clock-cells = <0>;
40 		clock-frequency = <300000000>;
44 		compatible = "fixed-clock";
45 		#clock-cells = <0>;
46 		clock-frequency = <600000000>;
50 		compatible = "fixed-clock";
51 		#clock-cells = <0>;
52 		clock-frequency = <100000000>;
53 		clock-accuracy = <100>;
57 		compatible = "fixed-clock";
58 		#clock-cells = <0>;
59 		clock-frequency = <24576000>;
60 		clock-accuracy = <100>;
64 		compatible = "fixed-clock";
65 		#clock-cells = <0x0>;
66 		clock-frequency = <533000000>;
70 		compatible = "fixed-clock";
71 		#clock-cells = <0x0>;
72 		clock-frequency = <262750000>;
73 		clock-accuracy = <0x64>;